t****t 发帖数: 6806 | 1 since tp-link router's IP is static (currently 192.168.0.1), you need to mak
e sure it is within master router's subnet, and without any conflict. otherw
ise A or B doesn't have the route to tp-link.
for example, if your master router is 192.168.1.1/24, all your computer know
how to visit 192.168.1.0-192.168.1.254. all other traffice will go to defau
lt gateway (192.168.1.1).
题。 |
|
i***g 发帖数: 127 | 2 【 以下文字转载自 EmergingNetworking 讨论区 】
发信人: ising (铱星), 信区: EmergingNetworking
标 题: 请教:关于modem总是关掉的问题
发信站: BBS 未名空间站 (Sat Mar 10 11:46:36 2007)
用的是comcast 的 cable
Motorola 的 SB5120 的modem
直接联到机器,总是会断。重启以后正常。
联到router (BELKIN),甚至一段不用也会断。
是不是有啥设置啊什么的?
多谢多谢! |
|
g*********e 发帖数: 42 | 3 isee, thanks
发信人: Nets (网), 信区: Programming
标 题: Re: C++小问题
发信站: BBS 未名空间站 (Sat Jul 28 10:00:50 2007), 转信
if u declare variables in switch statement, wrap the statement with {}
case 1: { A a1; } break;
case 2: { A a2; } break; |
|
r*****3 发帖数: 143 | 4 中文名: Windows Powershell 实战 (第2版)
原名: Windows PowerShell in Action, 2nd Edition
作者: Bruce Payette
图书分类: 软件
资源格式: PDF
版本: 英文文字版/更新源代码
出版社: Manning
书号: 9781935182139
发行时间: 2011年
地区: 美国
语言: 英文
简介:
内容介绍:
This expanded, revised, and updated Second Edition preserves the original's
crystal-clear introduction to PowerShell and adds extensive coverage of v2
features such as advanced functions, modules, and remoting. It includes full
chapters on these topics and also covers new language elements and
operat... 阅读全帖 |
|
r****y 发帖数: 26819 | 5 http://www.javaworld.com/javaworld/jw-01-2013/130107-developer-
age=1
Here is our guide to some of the more dominant tech generations in computer
history, as embodied by the programmers who gave them life. The list is far
from complete, but if you've been coding for any amount of time, you will pr
obably recognize many of these generational traits in yourself, your coworke
rs, and the programming community at large.
Punch-card programmers
The '60s-era computers received their instructions from a... 阅读全帖 |
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g****e 发帖数: 612 | 6 发信人: icic (isee), 信区: News
标 题: 早报 欧洲首次发射火星探测器
发信站: BBS 水木清华站 (Wed Jun 4 10:18:58 2003), 站内
(哈萨克斯坦拜科努尔法新电)欧洲星期一开始探测火星的首次行动,成功地使用俄罗
斯的“联盟”号火箭将“火星快车”(Mars Express)轨道飞行器送上太空,展开半年的
探测,试图揭开多年来的谜团:这颗红色的星球上到底有没有生命?
发射升空90分钟后,携带着“猎犬2号”(Beagle 2)登陆器的“火星快车”跟运载
火箭分离,开始了4亿公里的火星旅途。
如果一切进展顺利,“猎犬2号”将在圣诞节登陆火星,开始进行探测。“猎犬2号
”原是科学家达尔文探索生命起源时所乘船的名字。
欧洲宇航局科学主任索斯伍德说,这次成功发射,标志着欧洲已经加入了星际航行
的行列。“这是我们的第一步,我们有了一个跟好的开端。”
“猎犬2号”小组成员、英国的扎尔内凯教授告诉空中电视新闻,探测器到达火星前
,还有很长的路要走。
“火星快车”将花费不到七个月的时间飞到火星,它携带的七台相机、雷达和分光
计将从轨道上对火星表面进行探测 |
|
l**********1 发帖数: 5204 | 7 Matrix PDE Boolean network Bayesian network Game theory etc will belong
to Basic level =PhD student training
High dimensions Monte Carlo Markov Chain (MCMC), Hidden Markov models,
Kalman filters and Ising models
belong to middle level. PD training
One Book its any one chapter if you can read completely
then you should qualified basic level:
//www.ift.unesp.br/users/mmenezes/mathbio.pdf
---
Borwein integral sinc function Fourier Transform Higher level PI tenuring... etc.
//www.springerlink... 阅读全帖 |
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B******s 发帖数: 52 | 8 至于针对性,是针对什么呢????就因为LZ是数学或者计算的 就不用去理解生物
系统了??? 还是说就不用学一学生
物和物理了?
难道他是计算数学出身就该 整天摆弄toy model fit data 做一堆optimisations 和
predictions
你不管是啥背景的 你想做合成生物学 至少生物学的基础知识和问题就要了
解吧 难道生物学里的理论知识
就不用去学习了??
那你告诉我,你说针对性的数学都是什么,假如你知道用什么数学去解决特定的问题,
我觉得那就不会成为问题。。。
另外,不管是 systems biology 和 synthetic biology 跟 biology 没有区别,只不
过是生物学研究到达瓶颈后 自然提出来
的概念 (既然是瓶颈必然需要很多其他学科的知识和工具来试图解决问题)
各种领域的人都试过很多方法,就像你列举的那些 Matrix PDE Boolean network
Bayesian network Game theory
MCMC, HMM, Kalman... 阅读全帖 |
|
B******s 发帖数: 52 | 9 至于针对性,是针对什么呢????就因为LZ是数学或者计算的 就不用去理解生物
系统了??? 还是说就不用学一学生
物和物理了?
难道他是计算数学出身就该 整天摆弄toy model fit data 做一堆optimisations 和
predictions
你不管是啥背景的 你想做合成生物学 至少生物学的基础知识和问题就要了
解吧 难道生物学里的理论知识
就不用去学习了??
那你告诉我,你说针对性的数学都是什么,假如你知道用什么数学去解决特定的问题,
我觉得那就不会成为问题。。。
另外,不管是 systems biology 和 synthetic biology 跟 biology 没有区别,只不
过是生物学研究到达瓶颈后 自然提出来
的概念 (既然是瓶颈必然需要很多其他学科的知识和工具来试图解决问题)
各种领域的人都试过很多方法,就像你列举的那些 Matrix PDE Boolean network
Bayesian network Game theory
MCMC, HMM, Kalman... 阅读全帖 |
|
O******e 发帖数: 4845 | 10 Press Release
2012-10-08
The Nobel Assembly at Karolinska Institutet has today decided to award
The Nobel Prize in Physiology or Medicine 2012
jointly to
John B. Gurdon and Shinya Yamanaka
for the discovery that mature cells can be reprogrammed
to become pluripotent
Summary
The Nobel Prize recognizes two scientists who discovered that mature, specia
lised cells can be reprogrammed to become immature cells capable of developi
ng into all tissues of the body. Their findings have revolutionised our... 阅读全帖 |
|
l**********1 发帖数: 5204 | 11 名校 新人PhD 的 有关 关键词的 博士论文 最近三年到五年的 至少100篇
其全部PDF 文档或hard paper 都参考一下的话 可以看出点 如何建筑这幢楼的 端倪了
吧 (possible)
比如
citation from UBC 2009 PhD dissertation: "Particle Markov Chain Monte Carlo"
by
Roman Holenstein
full text pdf link:
HTTP: //www.cs.ubc.ca/grads/resources/thesis/May09/Holenstein_Roman.pdf
Monte Carlo methods have become the standard tool to solve many problems in
statistics and scientific computing. Examples are abound, and include
instances in
Bayesian statistics (posterior estimat... 阅读全帖 |
|
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Z********n 发帖数: 20 | 13 谢谢大家回复,主要是我们学校的商学院自己有人从stat转到marketing了,然后今年
自己申PHD(刚从engineering school master毕业),申的是OM,但其实对marketing
比较感兴趣一些,之前在学校做RA也涉及到OM和Marketing两个领域,要是读PHD的时候
能转就好了
另外有个问题求助大家一下,我这现在拿到了UCONN,UIOWA Tippie,McGill的商学院
(OM,quantitative method),还有UFL的工学院ISE的offer,其他有几个还在
Pending,如何选择能给个建议么? |
|
a*****g 发帖数: 19398 | 14 The Oklahoma Supreme Court ruled Tuesday that the state's repeal of the Comm
on Core State Standards was constitutional. Now, officials said, the state w
ill begin to craft its own rigorous standards for students.
http://www.tulsaworld.com/news/education/state-supreme-court-fi
re-repeal-constitutional/article_7d64eabe-3b0f-5ecf-8146-f5f9f91cf2e4.html
OKLAHOMA CITY — Only a few hours after hearing oral arguments, the Oklahoma
Supreme Court on Tuesday afternoon ruled a bill repealing Common Core s... 阅读全帖 |
|
a*****g 发帖数: 19398 | 15 IL 教师对 PARCC 发表的意见
【注:PARCC是基于Common Core的 Assessment】
Dear ICTM colleagues:
With the recent, extensive field test of PARCC test items now completed and
some sample items posted on the PARCC web site, teachers now have a better s
ense of the kinds of test items that PARCC will be asking. (Practice items
form the Grades 3-8 performance-based tests will be released in Fall 2014.)
I raise here one concern about plans for the performance (open response) ite
ms in the hope of generating some discuss... 阅读全帖 |
|
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m*******a 发帖数: 63 | 17 多谢!
what I still do not understand is the following:
In VHDL, if we use both rising_edge and falling_edge, an error would be
reported during compilation in Quartus or ISE. However, no error if we use
both negedge and posegde in Verilog. |
|
l*****x 发帖数: 3431 | 18 查查xilinx ISE IP core documents,讲得很详细 |
|
t*****e 发帖数: 666 | 19 xilinx ISE IP core documents
哪里可以找到? 多谢了 |
|
w****3 发帖数: 27 | 20 楼主能否写一个计数器到200归零循环计数的计数器代码来看看是否professional
style,
从module开始,endmodule结束。
verilog就好象C,
只是一门语言而已,
数字设计最重要的是算法,系统
但是这些,只要你的数学基础够,其实学不学都无所谓的。
估计楼主只是用FPGA做了一些verilog,要么是ISE,要么是Quartus。
VLSI还包含很多东西,从前端到后端,相关工具软件也很多。
可能可以出去应聘FPGA,但是如果VLSI可能差一点点。
没有别的意思,
只是希望大家能够相互学习交流补强自己。 |
|
s*******y 发帖数: 44 | 21 用XILINX ISE,SYNTHESIZE得到WARNING,
WARNING:Xst:1291 - FF/Latch is unconnected in block .在
线的说明说
Solution
When this warning occurs, a register or latch in your design has been
created, but the output is never connected or the signals or logic it drives
have been trimmed. Check the XST log for messages such as the following to
find signals that have been trimmed out of the design:
"WARNING:Xst:646 - Signal is assigned but never used."
可以我并没有说明里的WARNING,而且有关的信号用来驱动其他部分,并不 |
|
w****3 发帖数: 27 | 22 Signal is assigned but never used
你从my_sig开始追,
将其输出的相应信号慢慢理出来,
“没发现信号名的typo”这句话我不太明白是什么意思?
根据我的经验,还没有说找不到的。
而且一般这种错误有一个明显的特征,
就是会有一大堆相同的告警,告诉你都被trim掉或者prune掉了。
不过既然你是用FPGA,
建议你先用Synplify做综合,
术业有专攻,Synplify在综合这方面比较强,
而且相信能够帮你找到更多的问题。
ISE和Quartus在自己器件的P&R上面更强一些而已。 |
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a********g 发帖数: 42 | 23 另有可能xxx_reg的逻辑被其他信号代替了。 可以让ise生成一个verilog gate level
module. 如果simulation结果没变化的话, 不用太担心。
drives
to |
|
c*******o 发帖数: 62 | 24 当然可以,C#作GUI,C++作处理,ISE+System Generator/simulink搞定vhdl,还可以
再加个MySQL做数据保存生成报告,以上均可用express或D版,成本=0且相当好玩,花
多少时间就看你这几方面强不强了
了. |
|
l***g 发帖数: 1035 | 25 do you use ise?
check the pin out in the report first. |
|
|
k*******k 发帖数: 7 | 27 是可行的,把验证成功的verilog模块以IP core 的形式连到CPU上,就可以实现
PC 和模块的通讯,有wizard你可以用,具体的步骤网上有tutorial,Good luck~ |
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d*******l 发帖数: 2567 | 28 FPGA Designer – Garland, TX (6 month + contract)
* Seeking a contractor to perform FPGA development and FPGA integration.
* Minimum 5 years experience designing FPGA’s from design through
integration.
* Minimum 1 year experience with the following Designing with VHDL VHDL
Test Bench design and simulation Xilinx FPGA design with Virtex4 or Virtex5
family of FPGAs Use of Xilinx tools such as ISE, XST and Chipscope
* A Bachelor’s or higher degree in engineering. An Electrical or
Com |
|
c*******h 发帖数: 4883 | 29 看manual
买的什么chip就选什么speed |
|
m****l 发帖数: 42 | 30 用的器件型号是有速度级别的。property里当然要选正确的型号,实际上都有对应的选
项。 |
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l*****x 发帖数: 3431 | 31 印象中是越低越快,这个值是个裕度,-3相对最快 |
|
T******T 发帖数: 3066 | 32 Xilinx5, -1 (slowest), -2, and -3 (fastest)
For CPLD it's the opposite, denotes actual macrocell in->out delay. |
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c*******h 发帖数: 4883 | 33 用modelsim/activhdl这样的仿真器。但是后仿真的时候,hdl定义的内部信号不一定
available。 |
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a********e 发帖数: 381 | 34 在chip scope/signal tap里面提前加入pre-synthesis的观测节点。不过有可能被综合
掉。
timing analysis report看过没有?在altera的FPGA上能跑通的话,xilinx上跑不通可
能是IO assignment或者timing的问题 |
|
T******T 发帖数: 3066 | 35 I guess it would be more optimized, less strain on the ISE during place and
route and timing optimization. |
|
I***a 发帖数: 704 | 36 我这是用HandelC生成的verilog code,不存在什么约束文件
现在已经解决了,把LOC的那2行注释掉就可以了.
把LOC的那2行里的CLOCK和RESET改成Virtex 5里有的pin names也可以(e.g. A5, B6)
还有我看你挺内行的,能教我看下help文档吗? |
|
a********e 发帖数: 381 | 37 你改的这个就是约束,只是没有形成一个单独文件而已。
help文档怎么教啊....只要知道出问题了以后怎么help urself 查错就可以了,平时看
着也没什么用。 |
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w*****s 发帖数: 433 | 38 问几个基础问题
1)要做一个实时的数据通路,input有24位,output只有16位。不考虑用先编码后解码
的方法。其中要过一个ram,想到过用32 input/16output的ram,并设置不同的in/out
clk频率。那么是不是说input的clock就应该是output的clock的一半,才能保证数据的
实时传输?用ise自动生成这样的ram后,读写controller应该就分开写吧?
2)采样一个信号,比如用简单的一个2级串联的FF来采样(没有试过,不知可行否),
要求采样频率可调。我用不同divider生成了不同频率的clk,再用mux来选择这些clk,
会出问题否?因为听人说过不宜用mux来选择时钟信号。另外,如果我只是用behavior
来写一个可调的divider,实际生成的电路是不是也是用mux来选不同divider生成的不
同的clk?
3)现在要求采样长度可调。如果用上述FF的方法来做,怎样做到长度可调?比如设置
采样100个clk,采样50个clk,采样200个clk。。。。
问题都很基础,期待解答~谢谢! |
|
I***a 发帖数: 704 | 39 有谁用过Precision或者Synplify来综合FPGA的?
综合后的结果是以什么格式导入到Quartus或者ISE里的?
thanks. |
|
l*****x 发帖数: 3431 | 40 装好synplify pro以后,ISE里可以直接选择用synplify作综合的 |
|
d*******l 发帖数: 2567 | 41 start with Xilinx ISE VHDL examples(there are many under the installation
directory), go through the cycle of synthesis/map/PnR/bitGen a couple of
times, you might feel more confident. |
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i******y 发帖数: 48 | 42 FPGA/ASIC Design Engineer
Location: Southern California, CA
The FPGA/ASIC Design Engineer is responsible for the design of control, and
manufacturing chip systems utilizing advance high density FPGA products and
transition to ASIC/SoC design. This includes all areas of digital design of
FPGA/ASIC development including chip architecture, RTL, implementation, RTL
synthesis, validation, and lab bring-up and characterization. The Engineer
works with advanced development teams on developing next gen... 阅读全帖 |
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a********o 发帖数: 86 | 43 Here's the job description. Let me know if you know someone with good
analytical skills in a graduate CS or EE program who may be interested in
this internship. If you are interested, send an email to xqzhang1973@gmail.
com.
Job Title
Networking and Communications Systems Intern
Organization Name
Advanced Communications, FPGA Development and Silicon Technology
Detailed Description
This internship project is on solving wireline or wireless infrastructure
problems with ... 阅读全帖 |
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m********o 发帖数: 796 | 44 你的意思是说digital的layout是基于foundry layout的模块来的,所以你不用自己去
手动画再下一层的transistor了。
有没有什么资料或者demo能够让我了解这个具体的过程呢?比如说,我用verilog写个
最简单的dff,我想看看它用元件库里的layout出来是个什么样子的。用ISE能完成整个
流程么?从verilog到chip layout。
谢谢~~ |
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s*****t 发帖数: 987 | 45
ISE是xilinx的FPGA软件么? 我觉得不能看出来
FPGA是已经layout好的东西 |
|
f*********9 发帖数: 5 | 46 本人EE-VLSI master。主要想找Asic Design, Design Verification, Physical
Design.最近不知道是market不好,还是我简历有很大问题,投出去的简历没有任何回
应。求高
人指点,非常感谢。
简历如下:
============================================================================
=========
TECHNICAL SKILLS
Programming Language: Verilog, VHDL, SystemVerilog, C, C++, Perl
Applications: Design Compiler, PrimeTime, Encounter, NCSim, Virtuoso,
Modelsim
WORKING EXPERIENCE ... 阅读全帖 |
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l***r 发帖数: 12 | 47 招聘:C++ Developer – Akuna Capital – 上海
Leading Proprietary Trading Firm
Location: Shanghai
Key Skills: C++, Low latency, STL, Boost, Linux, UNIX, Multithreading
Website: www.akunacapital.com
Email: [email protected]
/* */
Who we are
Akuna Capital is a fast-growing trading house that specializes in derivative
market-making and arbitrage. We pair up experienced and talented traders
with industry-leading low latency IT, giving the company a huge advantage in
the dynamic screen-based trading sp... 阅读全帖 |
|