b****p
发帖数: 50 | 1 We're in need of a asic verification contractor who is good at OVM and PERL.
Please reply to this post. |
|
l******h
发帖数: 2 | 2 Highly reputational company with very competitive compensation for all
positions.
Please send in your resume and position/positions you like to apply to my
email address below.
h*******[email protected]
All resumes will be deliver to hiring manager directly. Act fast!
Thanks!
Silicon Engineering Group
Sr. Physical Design Timing Engineer
Timing (STA) Manager
Senior Physical Design Engineer
CAD Manager - Front-End Design and Verification
Sr. CAD Engineer - Place & Route / Physical Design Engineer
Sr. CA... 阅读全帖 |
|
l******h
发帖数: 2 | 3 Highly reputational company with very competitive compensation for all
positions.
Please send in your resume and position/positions you like to apply to my
email address below.
h*******[email protected]
All resumes will be deliver to hiring manager directly. Act fast!
Thanks!
Silicon Engineering Group
Sr. Physical Design Timing Engineer
Timing (STA) Manager
Senior Physical Design Engineer
CAD Manager - Front-End Design and Verification
Sr. CAD Engineer - Place & Route / Physical Design Engineer
Sr. CA... 阅读全帖 |
|
m******n
发帖数: 354 | 4 现在在做股指期权定价，用OVME pricer可以看到一个bloomberg volatility.对于每一
个买入日，每输入一个不同的到期日和一个不同的moneyness就会有一个新的vola. 我
想问的是，对于每一个买入日，有没有一个整个表格式的volatility surface呢？我查
到了一个，比如说30day_impvol_100%_moneyness,这是一个可以输到excel去的表格，
但是我对比了一下这个表格里的vola, 在同样的设置下和OVME定价器里的数字并不完全
一样，这是咋回事啊? OVME里的bloomberg vola是怎么来的啊? 恳请牛人们不吝赐教。 |
|
a**e
发帖数: 103 | 5 已经僻谣了. 不是MONTAIN LION, 是bobcat
A message from OAK VALLEY MIDDLE SCHOOL
Dear OVMS Parents:
Early this morning, news stations and the Sheriff’s department responded to
a report of a mountain lion; however, after further investigation it was
not a mountain lion, but a bobcat that was reportedly seen in the Ivy Gate
Community. Deputies investigated the area on foot and by helicopter, but no
bobcat was seen, and no other sightings were reported. If we have
additional reports, we will let you know.
... 阅读全帖 |
|
n******e
发帖数: 1046 | 6 We could use a couple of verification engineers with extremely good perl
experience.
We have another with strong OVM/UVM experience
We have a few storage companies looking for strong design and verification
experience.
We have another for strong post silicon experience, cabling, power, etc.
We have a Sr manager opening for Hardware with experience in the home router
gateway space.
I appreciate your time and if we can help you at your current company please
let me know.
Mel
Principal
408-345-9100... 阅读全帖 |
|
发帖数: 1 | 7 文思海辉 Pactera Technologies(www.pactera.com/en)热招 Pre-Silicon Validation
Engineer
接受OPT, H1b transfer
客户(项目): Intel
工作地点：Hillsboro, Oregon
Title: Pre-Silicon Validation Engineer
.
学历要求：BS or MS in Electrical Engineering, Computer Engineering or
Electrical and Computer Engineering
需要以下经验：
• Basic analog, mixed signal circuits
• Digital logic design and simulation using Verilog/VHDL
• 熟悉OVM/UVM or Verilog/VHDL
• high speed I/Os like DDR, PCI-express, USB or simila... 阅读全帖 |
|
h*******3
发帖数: 42 | 8 如果你对这个职位感兴趣，请跟我联系。
地点在 San Jose, CA
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Drive and adopt new verification methodologies and flows for efficiency
improvement
Assist with performance analysis and/or architecture
Desi... 阅读全帖 |
|
h*******3
发帖数: 42 | 9 【 以下文字转载自 EE 讨论区 】
发信人: huluwa123 (葫芦娃), 信区: EE
标 题: Open position
发信站: BBS 未名空间站 (Mon Apr 2 19:31:04 2012, 美东)
The position is in San Jose, CA.
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Drive and adopt new verification... 阅读全帖 |
|
l**t
发帖数: 10440 | 10 【 以下文字转载自 SanFrancisco 讨论区 】
发信人: lint (half life), 信区: SanFrancisco
标 题: Re: 【JOBS广告】04.01 -- 04.30
发信站: BBS 未名空间站 (Sat Apr 7 00:50:39 2012, 美东)
A big semiconductor company(Bay area, CA) is hiring Senior Design
Verification Engineer
Must:
EE MS, at least 2 years+
System Verilog/OVM or VMM
Plus:
DMA
PCIE
Please email your questions/resume to l******[email protected], thanks!
(We dont need new graduates, thanks) |
|
h*******3
发帖数: 42 | 11 下面这个职位贴了很久了，应者寥寥啊。有兴趣的话，给我站内信吧。
希望是有经验的。
This position is in San Jose, CA.
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Drive and adopt new verification methodologies and flows for efficiency
improvement
Assist with perfor... 阅读全帖 |
|
v***6
发帖数: 42 | 12 fresh grad, 除了5年的经验要求不满足, 懂DV的也不多吧, 好像学校里现在还不教DV
吧, 包括什么UVM/OVM/VMM |
|
m*d
发帖数: 6 | 13 My group is expanding in phone/tablet area, opening for couple of positions:
Engineer position:
Linux Driver developer, USB2/3 experience is plus. Familiar with android/OS/
kernel.
Hw/sw co design, FPGA emulation, debug
Consumer electronics System integration&debug, preferred phone/tablet
experience
RTL design, simulation, test bench of uvm/svm/ovm experience
FW experience
Manager position:
Program manager, at least 4years management experience.
Please drop me resume if have one or two match |
|
r******9
发帖数: 129 | 14 Requirements:
* MS/PHD degree in EE
* Verilog / System Verilog (OVM/UVM) / any scripting language
* 4+ years industry experience
* Mixed signal verification experience is a big plus
站内联系
Thanks |
|
n******e
发帖数: 1046 | 15 We could use a couple of verification engineers with extremely good perl
experience.
We have another with strong OVM/UVM experience
We have a few storage companies looking for strong design and verification
experience.
We have another for strong post silicon experience, cabling, power, etc.
We have a Sr manager opening for Hardware with experience in the home router
gateway space.
I appreciate your time and if we can help you at your current company please
let me know.
Mel
Principal
408-345-9100... 阅读全帖 |
|
p********i
发帖数: 96 | 16 感兴趣私信联系
Brief Description:
Design, develop, test and support Linux devicedrivers and RDS module
for Infiniband.
Detailed Description:
As a member of the Oracle Linux and Oracle VM division, you will take
an active role in the design, implementation, release, and support
for Infiniband device drivers, OFED stacks, and RDS module for Oracle kernel
and OVM. You will work closely with third party device vendor to jointly
design and develop software for Oracle products. You will be responsible
for... 阅读全帖 |
|
p********i
发帖数: 96 | 17 也是同组，欢迎new graduates
Job Description
Software Developer
Preferred Qualifications
The OVM infiniband group provides support for Mellanox OFED in Oracle Linux
, Oracle VM and engineered systems.
For this challenging role you have in-depth experience in the development of
Linux Kernel Device Drivers, PCI, and network. You have minimum 3 years in
a Linux Kernel & Networking environment. Know-How in Networking Device
Drivers
and knowledge in Virtualization is a must. Knowledge of Python is nice to
ha... 阅读全帖 |
|
s******e
发帖数: 52 | 18 有意者请给我发消息
Digital/Mixed Signal Design Engineer
Seeking a highly motivated and innovative digital/mixed signal design
engineer with strong theoretical and practical background in digital
circuits and FPGA design. Candidate with be part of a team responsible for
development of next generation AC/DC power management product and emulation
systems.
PRIMARY RESPONSIBILITIES
• Design and RTL coding of power management controller on FPGAs
from concept to production.
• Defining detailed... 阅读全帖 |
|
发帖数: 1 | 19 文思海辉 Pactera Technologies(www.pactera.com/en)热招 Pre-Silicon Validation
Engineer
接受OPT, H1b transfer
客户(项目): Intel
工作地点：Hillsboro, Oregon
Title: Pre-Silicon Validation Engineer
.
学历要求：BS or MS in Electrical Engineering, Computer Engineering or
Electrical and Computer Engineering
需要以下经验：
• Basic analog, mixed signal circuits
• Digital logic design and simulation using Verilog/VHDL
• 熟悉OVM/UVM or Verilog/VHDL
• high speed I/Os like DDR, PCI-express, USB or simila... 阅读全帖 |
|
h*******3
发帖数: 42 | 20 【 以下文字转载自 EE 讨论区 】
发信人: huluwa123 (葫芦娃), 信区: EE
标 题: Open position
发信站: BBS 未名空间站 (Mon Apr 2 19:31:04 2012, 美东)
The position is in San Jose, CA.
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Drive and adopt new verification... 阅读全帖 |
|
w*********s
发帖数: 277 | 21 4年functional verification经验。
主要是UVM/OVM，SystemVerilog，constrained random，functional coverage这些。
如果您的组或者你认识的组在招verification的职位，愿意refer的请pm，非常感谢！ |
|
d**********1
发帖数: 329 | 22 verification Engr
Masters degree (prefer) and 7 - 12 years LCD monitor/TV digital SOC design
verification related experience
Strong background in SOC verification. Expert on SOC system level
verification environment setup and implementation.
Extensive knowledge on System Verliog/OVM, Constraint Driven Verification (
CDV), Coverage Based Verification (CBV), Assertion Based Verification (ABV),
VMM.
Verification plan, testbench and testcases development
Audio/Video sub-system knowledge
Big plus to... 阅读全帖 |
|
l**t
发帖数: 10440 | 23 A big semiconductor company is hiring Senior Design Verification Engineer
Must:
EE MS, at least 2 years+
System Verilog/OVM or VMM
Plus:
DMA
PCIE
Please email your questions/resume to l******[email protected], thanks!
(We dont need new graduates, thanks) |
|
s******e
发帖数: 52 | 24 有意者请给我发消息
Digital/Mixed Signal Design Engineer
Seeking a highly motivated and innovative digital/mixed signal design
engineer with strong theoretical and practical background in digital
circuits and FPGA design. Candidate with be part of a team responsible for
development of next generation AC/DC power management product and emulation
systems.
PRIMARY RESPONSIBILITIES
• Design and RTL coding of power management controller on FPGAs
from concept to production.
• Defining detailed... 阅读全帖 |
|
