h*******y
发帖数: 896 | 1 send me your resume if your background matches this position very well
=======================================
Job Posting: Feb 15, 2011
Primary Location: US-TX-Austin-Parmer Lane (TX32)
Job: Product/Test
Education Level: Bachelor's Degree
Job Type: Experienced
HW/SW Manufacturing Test Engineer -
•Develop a test plan to provide test traceability back to product
requirements approved by project stakeholders
•Collaborate with the Business Unit, development teams, Customer
Engineering, ... 阅读全帖 |
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E*****a
发帖数: 757 | 2 恩。这个schematic不知道是不是和layout相关。
不过肯定是cap有关 |
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w*****s
发帖数: 433 | 3 最近一个向往已久的Qualcomm的一个电面,职位是 Digital Hardware Design Engineer (Baseband/FFA/SURF/PWB).虽然不是我学的IC的方向,但也非常希望能得到这个job.
这个position要求3年工作经验,我强调了我是new grad,但貌似他们也ok,给了个机会talk.
skill要求如下:
Candidates should have three to ten years experience designing consumer electronics, wireless devices and/or low power platforms. Solid electrical engineering, digital & analog circuit fundamentals and lab skills are a must. Strong written and oral communication and teamwork skills are required. Experience with digital c... 阅读全帖 |
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d*******d
发帖数: 3382 | 4 一般的电话面试，应该没法非常深入，所以至少准备好：
* brief self introduction
* resume上提过的所有东西，都要滚瓜烂熟，每个做过的project，都要有个summary/
story，并能够回答相关的细节
* 相关方面的fundemental。engineering的东西，很多东西万变不离其宗。
* 手头备好纸笔，随时准备开算，备好电脑，准备随时google（注意键盘声别被听到）
。回答面试问题，注意think aloud，把思路说出来，切忌不吭声闷头想花很多时间给
个正确答案，很多时候，面试看思路的方向对不对，intuition好不好。
* 准备一些关于职位公司的相关问题，如果给你机会问问题，可以趁机多了解一些这个
职位的requirement，这样为onsite复习准备的时候能有的放矢；同时要表现出对公司
和职位的兴趣。
Engineer (Baseband/FFA/SURF/PWB).虽然不是我学的IC的方向,但也非常希望能得到这
个job.
会talk.
electronics, wireless devices and/or low powe... 阅读全帖 |
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i****s
发帖数: 375 | 5 想用ambarella a5s 做一款运动摄像机，问了ambarella 公司，他们需要2.4万美元授
权费才能开发。他们提供完整的
软硬件参考设计。偶问下大牛们，这样设计成品需要多长时间啊？谢谢！
A5s Hybrid DV/DSC Camera Development Platform
The A5s Hybrid DV/DSC Camera Development Platform contains the necessary
tools, software, hardware and
documentation to develop a Hybrid DV/DSC Camera design.
Hardware Platform
° Main board with A5s and sensor board with C/CS mount lens ° Sensor :
Aptina, OmniVision, Sony — many
choices available
Software Development Kit (SDK)
° eSol ultron OS and deve... 阅读全帖 |
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b*******1
发帖数: 49 | 6 Hillsboro, Oregon.
有问题请跟贴问， 你的问题可能也是其他同学的问题。
RCG (新毕业生） only。
刚毕业一年之内的也行。
Business Group Overview
Employees in the Intel Architecture Group (IAG) deliver innovative
platforms across computing and communication segments including data centers
, mobile and desktop personal computers, handhelds, embedded devices and
consumer electronics. Intel's industry leading technology is used to create
integrated hardware and software solutions such as processors, chipsets,
communication radios, graphics proc... 阅读全帖 |
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s*******e
发帖数: 13 | 7 Here is the job description.
Will be part of analog design team for storage product. Design state-of-the-
art deep sub-micron CMOS analog front end for our high performance storage
products.
Masters degree plus 2~3 years of industry experience or PhD in the field of
analog IC design Experience in transistor-level design of one or more of the
following areas are required: ADC, DAC, Analog filter, VGA, wideband
amplifier, High performance voltage regulator, or PLL.
Strong understanding of analog c... 阅读全帖 |
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s**g
发帖数: 66 | 8 Analog expert Bob Pease dies in accident
Bill Schweber
6/20/2011 7:46 AM EDT
full article link:
http://www.eetimes.com/electronics-news/4217077/Analog-expert-B
Another sad loss for the analog-design community, and the engineering world
as a whole: Bob Pease, analog circuit-design expert, was killed in a car
crash Sunday, after leaving a private service for Jim Williams, who passed
away a week before (see here and here).
My colleague, Paul Rako of EDN, said:
"I was a good friend of Bob's. I w... 阅读全帖 |
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l********g
发帖数: 68 | 9 帮朋友转到版上,感兴趣的请直接和他联系。
Email: s*******[email protected]
Position Title: Junior Circuit Design Engineer (0-4 years’ experience)
Description/
Qualifications: RESPONSIBILITIES:
- High performance, low power custom circuit design in Digital-IP.
- Design, optimization, simulation and characterization of custom digital
circuits.
- Logic equivalence checking and transistor level function verification.
- 6T/8T/10T sram design.
- Library cells and datapath cells design.
- Knowledge of multi-port RF, ROM,... 阅读全帖 |
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l********g
发帖数: 68 | 10 Posted job opennings several weeks ago. Three opennings have been filled and
there are still several left. Please send your resume to sramcache@yahoo.
com ASAP if you are interested.
The employer sponsors H1B, and starts green card process immediately after
you join us in full time based on current policy.
Position Title: Junior Circuit Design Engineer (0-4 years experience)
Description/
Qualifications: RESPONSIBILITIES:
- High performance, low power custom circuit design in Digital-IP.
- Design... 阅读全帖 |
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i******y
发帖数: 48 | 11 A biomedical start-up company is looking for a person to fill a Hardware
test engineer/technician position, with 1 year contract to hire.
Location: Irvine, California.
local only.
1) familiar with basic op-amp based electronic circuits, RF circuits in the
DC to 100MHz range.
2) hands on experience with testing/debugging of circuits, VLSI chips.
3) know how to use schematic entry tools, PCB layout tools, like OrCad.
4) know how to use basic tools like scope logic analyzer, spectrum analyzer
for d... 阅读全帖 |
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d****y
发帖数: 76 | 12 【 以下文字转载自 JobMarket 讨论区 】
发信人: dooffy (dooffy), 信区: JobMarket
标 题: Opening of Circuit Design Engineer position at a Silicon Valley company
发信站: BBS 未名空间站 (Thu Nov 10 15:49:32 2011, 美东)
A reputable IC design company is now hiring Circuit Design Engineer with the
focus on transistor level circuit design. Please find the detailed job
description at the end of this message. If you are well qualified, we would
like you to join us as soon as you can. For those who are still in the
middle of degree pr... 阅读全帖 |
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b*****e
发帖数: 1193 | 13 prof说的有一定道理,但是上课不能保证你一定搞定工作.embedded sw 很依赖经验
embedded SW engr/firmware engr.这类工作比一般的CS出身的IT SW engr opening要
少,更依赖经验和行业积累.但是embedded sw engineer工作中要求的技能要比CS出身的
更强,rtos,c/c++, asm,matlab, C#,java, python,perl,make scripts,vhdl 都要能写
会用;熟悉emulators,多种microprocessors/dsp, 会各种测试仪器,知道如何测试软件
和硬件;读懂IC的datasheet,hw design schematics/pcb, 和硬件工程师能talk;懂各类
串并行总线,know-how on system integration;懂process and spec ,这个依赖于不同
行业
另外就是绿卡,好的embedded sw工作大部分都在defense,avionics,或者需要export control的企业,没卡,就没有敲门砖 |
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H***F
发帖数: 2501 | 14 1, create symbol .sym file for mos
2, creat model .sub file
3, in the schematic, place the symbol and use .inc command to include the .
sub file
4, done
一下是spice model，网上找了很多导入BJT Diode的，就是没找到cmos的，求大大们赐教
.MODEL MN NMOS
LEVEL=2
VTO=0.3V
LD=0.04U
UO=210
TOX=4E-09
+CGSO=230P CGDO=230P TPG=1 NSUB=3.7E17 MJ=0.4 CJ=1030U
+CJSW=130P MJSW=0.3 XJ=0.1U GAMMA=0.4 PHI=0.6 LAMBDA=0.2 |
|
d**g
发帖数: 1031 | 15 Both.
Application engineer support, customer design such as EVM board layout,
customized schematic and layout design, business development,market
development, etc. |
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m*****t
发帖数: 3477 | 16 主要区别在于device model本身。RF model要求更精确的parasitic RLC一般要用s-
parameter analysis来做extraction。对于FET的gate resistance，noise,，sub-R-
net等方面比较侧重。很多特制器件(inductor,varactor etc）model不scalable,一般采
用macro-model。如果RF device是III-V的，那么有专用的model来表征。
通用的analog/mixed-signal model注重基本DC，CV特征。对matching,monte-carlo，
leakage，tempCO及device linearity等feature要求高。Model一般采用compact(HV的
除外)，大多scalable。一般model corner会wider（比digital窄），便于IP reuse.
PDK本身自然也有差别，design rule, pcell spacing等等。
charaterization上其实区别可能最大，不是几句话能说清楚的。
如果你是PD... 阅读全帖 |
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i*****y
发帖数: 148 | 17 嗯，应该是很容易学
那个工程师可能是想画一个这样的wiring diagram好让technician接线用。我只用过几
种软件画circuit schematic |
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d**********r
发帖数: 6 | 18 gnuplot 不错，开源
octave 画图是基于gnuplot，开源
画schematics Adobe Illustrator 很好用 |
|
kn
发帖数: 2446 | 19 画schematic电路图的。可以做simulation啥的。
我老板给本科生freshmen开的intro to computer engineering课，用这软件做project |
|
a********m
发帖数: 92 | 20 小弟八月份毕业，开始找工快两个月了。感觉indeed和linkedin上虽然opening不少，
但是对fresh而言还是很艰难。我相信只要能找到第一份工作，以后的路应该会越走越
宽。希望版上各位过来人能给点建议，或者分享一点求职信息，在下感激不尽。
背景：
主要做过一些强电方面的design 和 testing
ECE Master Power Electronics
Experienced in the fields of:
- DCDC DCAC converter/inverter
- Linear & switch mode voltage regulator
- Magnetic components design
- Power MOSFET gate drive design
- Power electronics circuit modeling and analysis
- Electric vehicle traction drive system
- Wide bandgap semiconductor device (GaN & SiC) evaluation... 阅读全帖 |
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h********8
发帖数: 159 | 21 Responsibilities:
• Development of engineering specifications for battery control
systems based on market or customer requirements.
• Design both digital and analog electronic circuits for various
Battery Management System components.
• Design the interface of the battery packs to external equipment.
Ensure the designs comply with all relevant electrical codes and standards.
• Experimental testing, analyzing of test data, and test report
writing to record oper... 阅读全帖 |
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g*******7
发帖数: 820 | 22 本人很菜鸟.....坛子上各位请不要见笑
国内本科是power system的， 后来来美国读了master但是和power没关系，而是图像处
理， 就是用matlab编编程，很简单的毕业设计...然后就在当地的公司找到工作， 但
是方向又和学得完全不一样， 现在在公司title虽然也是electrical engineer，但是
做的东西都是些工厂里面control的， 比如说PLC啊，CNC啊，ROBOT啊 之类的，也会协
助maintanance 对machine trouble shooting。 感觉基础好薄弱， 这些都需要有很强
的硬件知识， 但是我就大二的时候摸了下那些电路元件， 早就忘光了.... 现在连读
懂schematic都有点困难， 总之做的各种不得心应手....又没人有点拨
因为年过27， 不得不考虑到以后要是有小孩子， 制造业做这种工作好辛苦， 天天都
要在车间， 所以在犹豫要不要再去读个本科老本行搞电力， 本科毕业已经五年了，基
本上知识学过的都忘了一大半了。。。。 不知道值不值得？ power如果没有绿卡，又
没有这方面的工作经历，好找工作吗？
还是继... 阅读全帖 |
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i******g
发帖数: 1444 | 23 一个二流学校PhD。刚毕业。
PhD方向是MRI的图像采集和重建。
MS的方向是做Hardware Design的。
我试着投了一些软件，硬件的工作，但是都没有什么大进展。现在的情况很尴尬，PHD
主要就是建模型啊，然后处理图像。主要用的是MATLAB。感觉工业界用得很少啊。C/C+
+学过，但是不常用。
硬件嘛，有好几年没有摸了。当年做的时候主要是偏数字和混合信号的电路（PLL里的
东西）schematic和layout都做。PCB板子也画过。
请问这里的大牛们，我可以找什么样的工作？或者我应该加强哪些方面，利于找工作
PS：我也不一定要干研发类的工作，一些bussiness development的工作也挺好的，不
知道哪里找entry level， 一般search 的Title都是什么。
谢谢大家了。。。 |
|
g****t
发帖数: 31659 | 24 你先把你喜欢的position 的job description拿出来,
然后把自己的简历改的match其中的关键字.
不然很可能连第一步筛选都过不了.
一个二流学校PhD。刚毕业。
PhD方向是MRI的图像采集和重建。
MS的方向是做Hardware Design的。
我试着投了一些软件，硬件的工作，但是都没有什么大进展。现在的情况很尴尬，PHD
主要就是建模型啊，然后处理图像。主要用的是MATLAB。感觉工业界用得很少啊。C/C+
+学过，但是不常用。
硬件嘛，有好几年没有摸了。当年做的时候主要是偏数字和混合信号的电路（PLL里的
东西）schematic和layout都做。PCB板子也画过。
请问这里的大牛们，我可以找什么样的工作？或者我应该加强哪些方面，利于找工作
PS：我也不一定要干研发类的工作，一些bussiness development的工作也挺好的，不
知道哪里找entry level， 一般search 的Title都是什么。
谢谢大家了。。。 |
|
n**********2
发帖数: 648 | 25 大家好,
我是在读EE硕士, 现在在规划课程. 有一门课程不解:
课名:ECE 756 - Computer-Aided Design for VLSI
单看课名很疑惑, 我不太清楚这门课究竟是用CAD软件来画版图或schematic-比如
cadence virtuoso来做IC设计? 还是更深一层的编写CAD软件本身?
我把course description和Topics也贴上来(见下), 尽管读完后我更不解-description
看起来像是编程而topics看起来像是画版图.
Brief description of the content of the course (Course Catalog Description)
implementation algorithms and data structures.
Topics covered: design styles, layout editors, symbolic compaction, module
generators, placement and routing, automatic synthesis, ... 阅读全帖 |
|
b***i
发帖数: 3043 | 26 schematic pls
use a buffer (op-amp) and see. Scope 50 ohms?
LC |
|
l********g
发帖数: 68 | 27 借用朋友的帐号发帖。
组里最近有openning.感兴趣的请站内回信。
Job Posting Title IRC97918
Job Title Senior Design Engineer
Detailed Description
Xilinx is looking for a highly qualified IC design engineer to join
the clocking hardware design team. This individual will work on digital
design of clock management blocks (eg, PLL, DLL) and clock distribution for
next generation FPGAs. The engineer will be involved in the entire design
process including RTL design, schematic gene... 阅读全帖 |
|
x*p
发帖数: 78 | 28 【 以下文字转载自 JobHunting 讨论区 】
发信人: xop (xop), 信区: JobHunting
标 题: RF Intern 职位 波士顿
发信站: BBS 未名空间站 (Sun Dec 15 16:44:24 2013, 美东)
EC711: Advanced RF technologies
Mitsubishi Electric Research Laboratories is looking for an intern to work
on the research area of advanced RF technologies. The ideal candidate should
be a senior Ph.D. student with good practical experience in microwave/RF
active circuits and/or module design. Familiarity with ADS for schematic,
layout design and Momentum simulation is r... 阅读全帖 |
|
x*p
发帖数: 78 | 29 Mitsubishi Electric Research Laboratories at Cambridge, MA is looking for an
intern to work on the research area of advanced RF technologies. The ideal
candidate should be a senior Ph.D. student with good practical experience in
microwave / RF active circuits and antenna design. Familiarity with ADS for
schematic, layout design and Momentum simulation is required. Deep
knowledge of active transistor circuits, radio front end, and 3D-EM circuit
simulation would be an asset.
Please send your appli... 阅读全帖 |
|
t*******c
发帖数: 306 | 30 考虑收ｎｅｗ ｇｒａｄ
Staff II Physical Design Engineer
Responsibilities include:
Interacting with the architecture team to develop a physical implementation
that can meet the schedule, power, frequency and area design targets.
Implementing the function using custom design techniques and enhanced
synthesis methodology
Insuring circuit based design specifications are met: setup and hold timing,
slew rates, noise, signal and power EM, dynamic and static IR, right sizing
of devices, VT and gate length select... 阅读全帖 |
|
d**g
发帖数: 1031 | 31 网上看来的, 我擦, 都不太会做.已经没法子跳槽啦.
1、我们公司的产品是集成电路，请描述一下你对集成电路的认识，列举一些与集成电
路
相关的内容（如讲清楚模拟、数字、双极型、CMOS、MCU、RISC、CISC、DSP、ASIC、
FPGA
等的概念）。（仕兰微面试题目）
2、FPGA和ASIC的概念，他们的区别。（未知）
答案：FPGA是可编程ASIC。
ASIC:专用集成电路，它是面向专门用途的电路，专门为一个用户设计和制造的。根据
一
个用户的特定要求，能以低研制成本，短、交货周期供货的全定制，半定制集成电路。
与
门阵列等其它ASIC(Application Specific IC)相比，它们又具有设计开发周期短、设
计
制造成本低、开发工具先进、标准产品无需测试、质量稳定以及可实时在线检验等优点
3、什么叫做OTP片、掩膜片，两者的区别何在？（仕兰微面试题目）
4、你知道的集成电路设计的表达方式有哪几种？（仕兰微面试题目）
5、描述你对集成电路设计流程的认识。（仕兰微面试题目）
6、简述FPGA等可编程逻辑器件设计流程。（仕兰微面试题目）
7、I... 阅读全帖 |
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d**g
发帖数: 1031 | 32 网上看来的, 我擦, 都不太会做.已经没法子跳槽啦.
1、同步电路和异步电路的区别是什么？（仕兰微电子）
2、什么是同步逻辑和异步逻辑？（汉王笔试）
同步逻辑是时钟之间有固定的因果关系。异步逻辑是各时钟之间没有固定的因果关系。
3、什么是"线与"逻辑，要实现它，在硬件特性上有什么具体要求？（汉王笔试）
线与逻辑是两个输出信号相连可以实现与的功能。在硬件上，要用oc门来实现，由于不
用 oc门可能使灌电流过大，而烧坏逻辑门。 同时在输出端口应加一个上拉电阻。
4、什么是Setup 和Holdup时间？（汉王笔试）
5、setup和holdup时间,区别.（南山之桥）
6、解释setup time和hold time的定义和在时钟信号延迟时的变化。（未知）
7、解释setup和hold time violation，画图说明，并说明解决办法。（威盛VIA
2003.11.06 上海笔试试题）
Setup/hold time 是测试芯片对输入信号和时钟信号之间的时间要求。建立时间是指触
发 器的时钟信号上升沿到来以前，数据稳定不变的时间。输入信号应提前时钟上升沿
（如... 阅读全帖 |
|
b*******m
发帖数: 72 | 33 see my article 6 years ago, time for people work in this industry to jump
the ship.
========================================================================
10 年前，Nortel, Lucent, Motorola 如日中天，谁能想到短短十年就被Huawei, ZTE
给灭了。
sorry too slow to type Chinese. back to 80's and 90's, Nortel was not just
designing telephone switch, they also design ASICs which goes to telephone
switch, like echo cancellation, SDH framer, CPU chipset(similar to north and
south bridge), and they work with chip maker(like Mot... 阅读全帖 |
|
b*******m
发帖数: 72 | 34 see my article 6 years ago, time for people work in this industry to jump
the ship.
========================================================================
10 年前，Nortel, Lucent, Motorola 如日中天，谁能想到短短十年就被Huawei, ZTE
给灭了。
sorry too slow to type Chinese. back to 80's and 90's, Nortel was not just
designing telephone switch, they also design ASICs which goes to telephone
switch, like echo cancellation, SDH framer, CPU chipset(similar to north and
south bridge), and they work with chip maker(like Mot... 阅读全帖 |
|
f*********9
发帖数: 5 | 35 本人EE-VLSI master。主要想找Asic Design, Design Verification, Physical
Design.最近不知道是market不好，还是我简历有很大问题，投出去的简历没有任何回
应。求高
人指点，非常感谢。
简历如下：
============================================================================
=========
TECHNICAL SKILLS
Programming Language: Verilog, VHDL, SystemVerilog, C, C++, Perl
Applications: Design Compiler, PrimeTime, Encounter, NCSim, Virtuoso,
Modelsim
WORKING EXPERIENCE ... 阅读全帖 |
|
f****i
发帖数: 20252 | 36 基本在schematic上验证，不在layout上验证。
除非有些射频信号要看看反射和泄漏 |
|
H***F
发帖数: 2501 | 37 那一半用orcad还是用ads验证呢？
基本在schematic上验证，不在layout上验证。
除非有些射频信号要看看反射和泄漏 |
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p********6
发帖数: 65 | 38 朋友组里面的职位，Manager 人很好，他们希望能找一个会讲中文的申请者，因为有时
需要跟大陆和台湾的公司打交道。可以直接公司网页申请，或者发信到freewheelin@
gmail.com
Hardware Engineer
Apply Now Apply now
Date: Jul 6, 2015
Location: Santa Clara, CA, US
Hardware Engineer
Location
US- CA, Santa Clara
Req # 26441
Functional Area
Supply Chain Management
Preferred Experience
Senior Level
Preferred Education
Bachelors Degree
Position Summary
Citrix is a leading provider of virtual computing solutions that help people
work and play from anywhere, on a... 阅读全帖 |
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g******u
发帖数: 3060 | 39 当年我是机械系毕业,研究生搞控制,一年以后去附近一大公司实习,我当时真的从来没
焊过电路!而且从来没见过真的电路板! 所以当然也没拿到return offer. 后来上班以
后边做边问,很快也独立从硬件到软件, schematic+layout+BOM+test从头到尾设计一个
产品.公司那点事情, 如果是世界上已经存在过类似的东西,学起来都不难,关键是别人
想和你合作就行.
return |
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j****9
发帖数: 2295 | 40 怎样把altium工程里的不同类别的文件放到不同的sub-repository folder中呢？
比如repository下有schematic，pdf，pcb，gerber几个文件夹。
版本控制软件是SVN。 |
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y***0
发帖数: 65 | 41 • Haptic actuator design and integration
• Schematic design of boards and flexible assemblies
• Develop software and scripts for automation of engineering tasks
• Contribute to the development of system models
• Author engineering requirements and specifications
• Perform failure mode analysis and problem solving
• Characterize and validate haptic module performance
• Data analysis on large data sets to identify trends and correlations
opening不是很多但... 阅读全帖 |
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h*********1
发帖数: 37 | 42 地点： 宾州匹兹堡
公司： 大型国际公司变频器研发部，业内领先
要求： 如下 （补充： 需要有毕业后5年以上实际工作经验）
联系： 请发电邮: [email protected]
/* */
谢谢！
[email protected]
/* */----------
Specific Requirements
-Design and implement hardware & software for real-time embedded devices
Circuit design, developing schematics, circuits analyzing and testing, PCB
components selection, design for manufacturing, PCB lifetime managing.
- Will be required to provide a wide variety of product development
disciplines including Digital, Analog, as it... 阅读全帖 |
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l********g
发帖数: 68 | 43 Xilinx clocking group has opening. I can help to forward resume to hiring
manager.
Digital circuits design position. Candidates should be fresh graduate or
have 1~3 years working experience.
主要是semi-custom design. 要求懂RTL coding, schematic capture and spice
simulation. Synthesis and place&route is a plus, 但也可以入职后培训。
Candidate will work on blocks like global clocking and all digital PLL. |
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e****o
发帖数: 176 | 44 最近想换一下工作. 2年工作经验. 现在小公司, Schematic, PCB都做. 不是IC设计.
请问湾区有哪些比较好的硬件公司能推荐一下? 我就知道一个A家, 网投简历后根本不
理我.
求推荐公司. 多谢. |
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e****o
发帖数: 176 | 45 我前后大约有3年工作经验, 主要是做Schematic, PCB设计,用到很多USB 3.0,
Ethernet, DDR3, 电源设计用到SMPS, LDOs.
最近投了G家 consumer hardware的几个职位, 一直没有消息.
这几个职位很match, 请哪位帮着内推一下.
非常感谢. |
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b*******7
发帖数: 82 | 46 以下是一个猎头发来的消息，在Minnesota.
如果有兴趣请站内留言，留下电话，EMAIL 我转发给猎头。
Responsible for design wastewater treatment systems (including SBR,
Oxidation Ditch, Fixed Film Media, and DAF systems) following receipt of
purchase order.
Prepare approval submittals information, certified drawings, and O&M Manuals
consistent with the project plans and specifications and scope of supply.
Major Areas of Responsibility:
Project Engineering
Read and understand customer project drawings including electrical
schematics, mecha... 阅读全帖 |
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f*******e
发帖数: 58 | 47 申请了local 的water reclamation 的environmental specialist 的位子，需要考试
，考试内容为
The written test will assess candidates' knowledge, skill and ability in
areas such as chemistry and biology; field sampling techniques; mathematical
calculations; principals and practices of QA/QC; District Ordinances
including the current User Charge Ordinance (available on the District's
website); job related safety, including OSHA guidelines; supervision;
interpretation of schematics and site drawings; and written communic... 阅读全帖 |
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f*******e
发帖数: 58 | 48 申请了local 的water reclamation 的environmental specialist 的位子，需要考试
，考试内容为
The written test will assess candidates' knowledge, skill and ability in
areas such as chemistry and biology; field sampling techniques; mathematical
calculations; principals and practices of QA/QC; District Ordinances
including the current User Charge Ordinance (available on the District's
website); job related safety, including OSHA guidelines; supervision;
interpretation of schematics and site drawings; and written communic... 阅读全帖 |
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c*s
发帖数: 2145 | 49 THE KEY POINT HEREIN as I think is to what extent the author follow the origin
data by using a schematic.
In many cases, the authors were seen to oversell their work by drawing a
explicit procedure, intermidiate state, and product. I often see some very
questionair images accompamnied with, however, a very impressive cartoon. This
happens most frequently in molecular assembly reearch.
难
的 |
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d****y
发帖数: 53 | 50 schematically (T is a discrete random variable; denote its prob's as p_T, T=
1,2,... \infinity)
compute the moment-generating-function on both sides, one gets
\sum_T=1^{\infinity} p_T [1/(1+u)]^T = MGF_of_B(u) = MGF_of_B( (1+u) -1 )
expanding both sides of the above equation as a power seris in y=(1+u) gives
you p_T.
Additional comments:
Interpretation of B: it is the arrival-time of the T-th event for a poisson
process. |
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