m****l
发帖数: 17 | 1 I have two opening in my group:
One principal level with
1. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Another one sr. principal level with
1. CMOS Image pixel design experience
2. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Need Citizenship/PR
Send me email |
|
m****l
发帖数: 17 | 2 I have two opening in my group:
One principal level with
1. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Another one sr. principal level with
1. CMOS Image pixel design experience
2. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Need Citizenship/PR
Send me email |
|
m****l
发帖数: 17 | 3 I have two opening in my group:
One principal level with
1. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Another one sr. principal level with
1. CMOS Image pixel design experience
2. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Need Citizenship/PR
Send me email |
|
m****l
发帖数: 17 | 4 I have two opening in my group:
One principal level with
1. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Another one sr. principal level with
1. CMOS Image pixel design experience
2. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Need Citizenship/PR
Send me email |
|
m****l
发帖数: 17 | 5 I have two opening in my group:
One principal level with
1. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Another one sr. principal level with
1. CMOS Image pixel design experience
2. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Need Citizenship/PR
Send me email |
|
s***d
发帖数: 15421 | 6 国内模拟50w不稀奇吧。做手机太难的话，做cable application，或者high speed
serdes 也能发大财。话说high speed serdes是不是被华为垄断了，国内家家都fiber
入户，免费送Modem。估计是北加华为组做的soc。 |
|
m****l
发帖数: 17 | 7 I have two opening in my group:
One principal level with
1. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Another one sr. principal level with
1. CMOS Image pixel design experience
2. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Need Citizenship/PR
Send me email |
|
w7
发帖数: 76 | 8 代友人小孩问个问题。graduate school 面临选老板, 大老板偏 serdes design。现在
主攻serdes for automobile。二老板做sensor，好像超声波还是什么图像传感。好像
都是IC design。不知道那个方向更好些。虽然劝告转cs，但小孩自己对编程没那么大
兴趣。谢谢。 |
|
w7
发帖数: 76 | 9 刚回复了，好像出了问题。
我觉得serdes要是低速就是数字了，高速的不是。
比起来serdes，觉得传感器可能稍好些吧。但我猜做到后面也就是做device physics了
。不管哪个方向，现在扎进去，三两年毕业出来ic工作形势还是个未知。 |
|
g*****d
发帖数: 210 | 10 两个都不容易
感觉射频难做， serdes复杂
不过现在好象serdes好找工作 |
|
s****h
发帖数: 3979 | 11 I found this jar file:
https://github.com/ogrodnek/csv-serde
However, got error saying the jar file doesn't exist when I run
add jar /user/jarTemp/csv-serde-1.1.2-0.11.0-all.jar;
Any idea?
For Cloudera, the jar file(s) has to be in specific path?
Thanks. |
|
x***o
发帖数: 127 | 12 算了吧。吹牛逼容易。给你一个数据对比，你就知道了：华为去年获国家科技一等奖的
是 10G serdes。 美国两年前就是30-40G已经商用了。华为手到擒来，这种牛逼吹吹可
以涨涨志气，但是要把自己吹晕了，那就更没戏了。
我不怀疑WI-FI华为已经攻克，性能一流，这个算是相对“低速”，发展了很多年了。
真正最尖端的器件技术，美国是一直有严格的控制的。现在相关STEM专业都控制了。 |
|
x***o
发帖数: 127 | 13 吹牛逼的自主知识产权都泛滥了。国家自然科学一等奖，2014年，还给了清华“透明计
算”。
别人拿过来的IP集成一下，自主理解后掌握彻底创新的，差别大得很。
最牛逼的人物在美国的几所大学和超级强大几个公司里面，华人都进不去，基本上封锁
住了。
假设华为里面养了一堆天才牛人，自己这么折腾几年，这么几年就变成了50G大拿？能
把工具用好，知道仿真模拟工具的各自优缺点，这个就要不少年。更何况背后的东西，
没人指点，摸索起来很难。
华为算是国内研发投入很厉害的，挖人也很用钱砸。系统集成方面很厉害，效率非常高
，商业方面有竞争力，还有国家的基金砸和银行支持，是高科技领先突破的的希望。但
是五毛式的捧杀很无聊。
任正非很清楚，是备胎。其实做备胎也没啥，只要认真做事，用钱砸，砸到一个两个人
物领入正确的道路，之后备胎也可以做的比正胎好，这只是个时间问题。
很多方面，容易的已经突破了，难的东西，尽量追赶就是了。如果真的彻底掌握了，能
够自创手到擒来 高速ADC， SERDES，高性能RF，那么美国的电子设计高科技基本上就
没有啥优势了，甚至以后有希望追平。
但是这种东西，不是简单的买来集成，需要静下心来... 阅读全帖 |
|
m****s
发帖数: 18160 | 14 【 以下文字转载自 EE 讨论区 】
发信人: kyliang (Kevin), 信区: EE
标 题: Hiring Experienced Logic Designers (Nvidia)
发信站: BBS 未名空间站 (Fri Nov 15 13:45:45 2013, 美东)
I am with Nvidia and am hiring 2 logic designers in analog mixed signal team
. Here is the job description. Will consider RTL designer if is interested
to learn the new things. I am the hiring manager. If you are interested,
please send your resume directly to my personal email k****[email protected] or
apply to Nvidia.com (job ID 1643124). No recruiters pleas... 阅读全帖 |
|
n*********h
发帖数: 98 | 15 代友转发，请勿回信箱，直接发联系人的email。谢谢！
================================================
We are a fast-growing medium-size company located in Silicon Valley,
and currently have a few job openings in analog/mixed-signal design
for high-speed SerDes.
Ideal candidates should have previous circuit-design experiences in at
least one of the following: CDR, PLL/DLL, (wireline) transmitter, data
converter; all levels of experiences are welcome.
The company offers a friendly work environment and opportunities to
wor... 阅读全帖 |
|
w******t
发帖数: 441 | 16 Serdes/High Speed analog-mixed signal IC applications engineer Position
located in Southern California
MINIMUM REQUIREMENTS:
- Extensive experience in Tx, Rx, CDR, PLL for high speed IO interfaces.
- Experience with optical communication system
- Knowledge of optical transponder, tranceiver
- Experience in chip bring-up, debugging and use of lab instrumentation is
required.
- Knowledge in system level timing budget, signal integrity, and power
integrity is a plus.
- BS or MS in Electrical Engine... 阅读全帖 |
|
f****y
发帖数: 33 | 17 本公司是位于上海附近的一家从事高速网络集成电路开发设计的初创公司,主要产品是
高端网络交换机芯片.我们迫切寻找在该领域工作多年,有丰富经验的海外优秀人才加盟
我公司.
我们现特招聘交换机芯片高级系统架构师,交换机芯片高级ASIC设计和验证主管,软件设
计和测试主管.我们的待遇优厚.如有兴趣,或要了解更多详情, 可以站内联系我.
职位详细介绍：
1) Ethernet Switch System Senior Architect
Job Description:
Responsible for defining ASIC SOC chip & system architecture for Ethernet
communications switch devices. The candidate must have eight or more years
experience with silicon device architectures, with at least five years
experience with Ethernet communications devices... 阅读全帖 |
|
m**c
发帖数: 168 | 18 即将有一个qualcomm的analog design的面试，job responsibility主要包括一下内容，
Design interface circuits including TX, RX, CDR, PLL and SerDes functions.
Design analog sub-blocks for Display drivers and PMIC,including DC-DC
converter,(LDO), ADC and DAC.
想听听大家的建议，收到大家的祝福，非常感谢。 |
|
t****t
发帖数: 6806 | 19 要求: 通信背景, phd, or MS with experience, 熟悉通信理论, 信号处理, 通信系统
设计, C/C++和matlab.
高速信号处理, serdes, ethernet, 数字设计的经验或与数字设计合作的经验 are
plus.
站内信联系. |
|
A*******s
发帖数: 23 | 20 Email your resume and job title to a****************[email protected]
Full position list:
Timing (STA) Manager
Sr. Physical Design Engineer - PnR
Physical Design Engineer - STA
Physical Design Engineer - Timing Spice
Physical Design Engineer - PDV
Physical Design Methodology Engineer
Signal Integrity Engineer
Serdes PCS Design Engineer
IC Clock Design Engineer
Analog IP Engineer
Analog IP Validation Engineer
Design Verification Engineer
Silicon Validation-Debug/Triage Engineer
Silicon Validation Engin... 阅读全帖 |
|
A*******s
发帖数: 23 | 21 Email your resume and job title to a****************[email protected]
Full position list:
Timing (STA) Manager
Sr. Physical Design Engineer - PnR
Physical Design Engineer - STA
Physical Design Engineer - Timing Spice
Physical Design Engineer - PDV
Physical Design Methodology Engineer
Signal Integrity Engineer
Serdes PCS Design Engineer
IC Clock Design Engineer
Analog IP Engineer
Analog IP Validation Engineer
Design Verification Engineer
Silicon Validation-Debug/Triage Engineer
Silicon Validation Engin... 阅读全帖 |
|
w*********b
发帖数: 25 | 22 【 以下文字转载自 EE 讨论区 】
发信人: wirelessjob (jobhunter), 信区: EE
标 题: offer 选择
发信站: BBS 未名空间站 (Fri Mar 15 11:52:54 2013, 美东)
一个是华为，做光纤通信方面，另一个是LSI的Serdes方面，都是做系统建模，算法开
发等，华为的偏research一些，LSI的主要是做产品开发，待遇也差不多。因为本人对
这两个领域都不太熟悉，恳求建议，哪个的职业发展前景会稍微好点？ |
|
k*****g
发帖数: 2 | 23 I am hiring 2 logic designers in analog mixed signal team. Here is the job
description. Will consider RTL designer if is interested to learn the new
things. I am the hiring manager. If you are interested, please send your
resume directly to my personal email k****[email protected] or apply to Nvidia.com
(job ID 1643124). No recruiters please.
MINIMUM REQUIREMENTS:
- Working knowledge and experiences of logic design, verification and RTL
modeling.
- Working knowledge of custom digital circuit design.
-... 阅读全帖 |
|
n*********h
发帖数: 98 | 24 代友转发，请勿回信箱，直接发联系人的email。谢谢！
================================================
We are a fast-growing medium-size company located in Silicon Valley,
and currently have a few job openings in analog/mixed-signal design
for high-speed SerDes.
Ideal candidates should have previous circuit-design experiences in at
least one of the following: CDR, PLL/DLL, (wireline) transmitter, data
converter; all levels of experiences are welcome.
The company offers a friendly work environment and opportunities to
wor... 阅读全帖 |
|
t****t
发帖数: 6806 | 25 usb3基本上是LVDS的serdes, 发送端是800~1200mVpp, 低压版是400~1200mVpp.
接收端要求100mVpp的eye height. |
|
k******d
发帖数: 48 | 26 please forward your resume to [email protected]
(function(){try{var s,a,i,j,r,c,l,b=document.getElementsByTagName("script");l=b[b.length-1].previousSibling;a=l.getAttribute('data-cfemail');if(a){s='';r=parseInt(a.substr(0,2),16);for(j=2;a.length-j;j+=2){c=parseInt(a.substr(j,2),16)^r;s+=String.fromCharCode(c);}s=document.createTextNode(s);l.parentNode.replaceChild(s,l);}}catch(e){}})();
/* ]]> */
Embedded System Software Architect - SoC Development (IRC104844)
https://www.linkedin.com/jobs2/cap/... 阅读全帖 |
|
c****n
发帖数: 86 | 27 华为海思招聘:
1. GaAs Process, Semiconductor Process, Pilot Production, ATE
2. Mobile AP/Baseband/PMIC/automotive IC
3. High Speed SerDes Testing
San Diego or Bay Area.
Senior-level professionals in these areas are welcomed to contact me.
Thanks! |
|
c****n
发帖数: 86 | 28 华为海思招聘:
1. Semiconductor Process, Pilot Production, ATE
2. Mobile AP/Baseband/PMIC/automotive IC
3. High Speed SerDes Testing
San Diego or Bay Area.
Senior-level professionals in these areas are welcomed to contact me.
Thanks! |
|
x**********e
发帖数: 155 | 29 【 以下文字转载自 EE 讨论区 】
发信人: xiaofeixiake (Light be with you.), 信区: EE
标 题: offer选择
发信站: BBS 未名空间站 (Sun Apr 3 10:00:20 2016, 美东)
offer1: 小的startup， 印度公司， 中国manager。 做high speed serdes， 主要提
供IP，用14nm，22nm 工艺。
offer2: 中型公司， 中国manger。 analog sensor组。 会做LCOS 显示的芯片。 偏
digial， memory， 工艺大概65nm。
compensation都差不多， 本人刚有娃的大妈一枚。 打算再生一个娃。 |
|
g*********e
发帖数: 14401 | 30 也不是没有。做eda 要用递归和dp，还有topi sort
做parser (不一定是编程语言的parser，sql parser或者自己invent出来的query
language parser) 要用递归。
二叉树就更多了。做ml, 要搞一个压缩boosting tree的算法 那就是leetcode里serdes
二叉树。
反正做后端的话，每家公司都会遇到类似的活，多多少少
打你 |
|
m**********s
发帖数: 518 | 31 我的问题是：谁工作中用到了
你回答的是：这些有用
我原本就没说它们没用
这个逻辑清楚不
否则我可以面试码农的时候问近世代数，它有用啊
serdes |
|
h*********n
发帖数: 11319 | 32 我们做compiler的全是递归
二叉树真心没见过，谁tmd自己写这玩意
serdes |
|
j***w
发帖数: 489 | 33 都是niche area。我这么多年就没写过tree, graph, sorting, parsing等等，最多用
下别人的库。
serdes |
|
|
m****s
发帖数: 18160 | 35 【 以下文字转载自 EE 讨论区 】
发信人: kyliang (Kevin), 信区: EE
标 题: Hiring Experienced Logic Designers (Nvidia)
发信站: BBS 未名空间站 (Fri Nov 15 13:45:45 2013, 美东)
I am with Nvidia and am hiring 2 logic designers in analog mixed signal team
. Here is the job description. Will consider RTL designer if is interested
to learn the new things. I am the hiring manager. If you are interested,
please send your resume directly to my personal email k****[email protected] or
apply to Nvidia.com (job ID 1643124). No recruiters pleas... 阅读全帖 |
|
|
|
f****y
发帖数: 33 | 38 本公司是位于上海附近的一家从事高速网络集成电路开发设计的初创公司,主要产品是
高端网络交换机芯片.我们迫切寻找在该领域工作多年,有丰富经验的海外优秀人才加盟
我公司.
我们现特招聘交换机芯片高级系统架构师,交换机芯片高级ASIC设计和验证主管,软件设
计和测试主管.我们的待遇优厚.如有兴趣,或要了解更多详情, 可以站内联系我.
职位详细介绍：
1) Switch System Senior Architect
Job Description:
Responsible for defining ASIC SOC chip & system architecture for Ethernet
communications switch devices. The candidate must have eight or more years
experience with silicon device architectures, with at least five years
experience with Ethernet communications devices. Must be... 阅读全帖 |
|
f****y
发帖数: 33 | 39 本公司是位于上海附近的一家从事高速网络集成电路开发设计的初创公司,主要产品是
高端网络交换机芯片.我们迫切寻找在该领域工作多年,有丰富经验的海外优秀人才加盟
我公司.
我们现特招聘交换机芯片高级系统架构师,交换机芯片高级ASIC设计和验证主管,软件设
计和测试主管.我们的待遇非常优厚.如有兴趣,或要了解更多详情, 可以站内联系我.
职位详细介绍：
1) Ethernet Switch System Senior Architect
Job Description:
Responsible for defining ASIC SOC chip & system architecture for Ethernet
communications switch devices. The candidate must have eight or more years
experience with silicon device architectures, with at least five years
experience with Ethernet communications devic... 阅读全帖 |
|
z*****h
发帖数: 547 | 40 我觉得这个完全看组吧，通常一篇ISSCC就是一篇JSSC
只要学校做的方向不是工业界的热门方向，例如高速ADC和Serdes
抑或自己是偏TGHz毫米波电路的
老板懂行给点指导，加上自己搞一点花头
两篇ISSCC+两篇JSSC完全有可能
再和师兄师弟互挂几篇，十篇也不是不可能的 |
|
z*****m
发帖数: 66 | 41 My group has multiple openings for senior analog design engineer, with the
description shown below. I can help recommend you to the people in charge
here. If you like, you can sent me a message to t***********[email protected].
This position is for a senior analog designer with experience in the high
speed signal path area. This designer will support the high performance
switch and possibly some SERDES PHY development. Experience in the areas of
high speed analog signal processing is required. This i... 阅读全帖 |
|
r*******r
发帖数: 308 | 42 bay area. and analog serdes design. |
|
w*********b
发帖数: 25 | 43 【 以下文字转载自 EE 讨论区 】
发信人: wirelessjob (jobhunter), 信区: EE
标 题: offer 选择
发信站: BBS 未名空间站 (Fri Mar 15 11:52:54 2013, 美东)
一个是华为，做光纤通信方面，另一个是LSI的Serdes方面，都是做系统建模，算法开
发等，华为的偏research一些，LSI的主要是做产品开发，待遇也差不多。因为本人对
这两个领域都不太熟悉，恳求建议，哪个的职业发展前景会稍微好点？ |
|
|
c****n
发帖数: 86 | 45 【 以下文字转载自 JobHunting 讨论区 】
发信人: crobin (铜豌豆), 信区: JobHunting
标 题: 华为海思招聘:GaAs Process, Semicon. Process, Pilot Production, ATE
发信站: BBS 未名空间站 (Fri Sep 18 13:32:02 2015, 美东)
华为海思招聘:
1. GaAs Process, Semiconductor Process, Pilot Production, ATE
2. Mobile AP/Baseband/PMIC/automotive IC
3. High Speed SerDes Testing
San Diego or Bay Area.
Senior-level professionals in these areas are welcomed to contact me.
Thanks! |
|
c****n
发帖数: 86 | 46 【 以下文字转载自 JobHunting 讨论区 】
发信人: crobin (铜豌豆), 信区: JobHunting
标 题: 华为海思招聘:GaAs Process, Semicon. Process, Pilot Production, ATE
发信站: BBS 未名空间站 (Fri Sep 18 13:32:02 2015, 美东)
华为海思招聘:
1. GaAs Process, Semiconductor Process, Pilot Production, ATE
2. Mobile AP/Baseband/PMIC/automotive IC
3. High Speed SerDes Testing
San Diego or Bay Area.
Senior-level professionals in these areas are welcomed to contact me.
Thanks! |
|
g********n
发帖数: 2314 | 47 这个电路是serdes还是逻辑电路？现在硬件的start up成功的机会不如以前了。门槛太
高。 |
|
c****n
发帖数: 86 | 48 【 以下文字转载自 JobHunting 讨论区 】
发信人: crobin (铜豌豆), 信区: JobHunting
标 题: 华为海思招聘:GaAs Process, Semicon. Process, Pilot Production, ATE
发信站: BBS 未名空间站 (Fri Sep 18 13:32:02 2015, 美东)
华为海思招聘:
1. GaAs Process, Semiconductor Process, Pilot Production, ATE
2. Mobile AP/Baseband/PMIC/automotive IC
3. High Speed SerDes Testing
San Diego or Bay Area.
Senior-level professionals in these areas are welcomed to contact me.
Thanks! |
|
|
