m********o
发帖数: 796 | 1 在计算机体系结构领域曾经发生过一件很有意思的事：早期的（现在其实也是）CPU生
产出来以后，都会有机构拿一些testbench（一些特殊的程序，测试一些特定的指令及
混合）去测试这些CPU的性能，做成分数比较。各大厂商绞尽脑汁想提高分数，后来大
家殊途同归想到了同一个办法：既然在系统级提高性能很难，那干脆研究那些
testbench的特性，针对这些testbench进行专门设计强化性能。于是，大家分数都高了
，但一旦大规模使用，时间一久又露陷了。。
这个历史是我的computer architecture老师说的，他是我读书时学校工程学院的dean
。故事眼熟么？engineer个个都是玩数据的老手，phd背景的更是如此，数据？问问phd
engineer谁会相信数据？我以前所在领域的引用次数第一的一篇期刊是我师兄09年一
手炮制，直到11年该领域所有论文都还在引，而我师兄10年就因为被老板发现而被fire
了(但老板却没撤论文)...
什么都没有常识可靠～ |
|
I***a
发帖数: 704 | 2 问题解决了，
原因是Xillinx ISE提供的SIMPRIM timing model有问题，
在testbench里输入需要等待1个offset time才能变化，否则就会出错(比如从 25 ns就
开始变化)
Xillinx ISE自动生成testbench的Wizard里就有这个offset选项
把原来testbench的起始时间点推后100 ns(从 125 ns开始变化)，
就完全正常了 |
|
l******h
发帖数: 2 | 3 Highly reputational company with very competitive compensation for all
positions.
Please send in your resume and position/positions you like to apply to my
email address below.
h*******[email protected]
All resumes will be deliver to hiring manager directly. Act fast!
Thanks!
Silicon Engineering Group
Sr. Physical Design Timing Engineer
Timing (STA) Manager
Senior Physical Design Engineer
CAD Manager - Front-End Design and Verification
Sr. CAD Engineer - Place & Route / Physical Design Engineer
Sr. CA... 阅读全帖 |
|
n*********h
发帖数: 98 | 4 有意者请站内联系。
The engineer will join automatic random testbench generation team of
Verification Group, Synopsys Inc., in Mountain View, California. This team
leads the development of constraints solver, which generates constrained
random stimuli as input to logic simulator (like VCS from Synopsys).
• You will be responsible for the research, design, development and
debug of current constraints solver, to further improve its performance and
keep industrial leadership.
• You will hav... 阅读全帖 |
|
w****8
发帖数: 33 | 5 因为项目需要，
需要找一个contractor做Verification工作，
三个月。
需要
1. 用UVM bring up testbench from scratch,
2. write testcases
3. documentation
4. migrate UVM testbench
所以需要有多年工作经验，或者你很自信你对UVM很熟。
工作地点：CA, SAN JOSE, H公司。
有意者可以发简历到[email protected]/* */
我会把你的简历转给我的manager。
有效期可能比较短，
因为其实HR已经开始在通过中介找人了。
谢谢 |
|
l******h
发帖数: 2 | 6 Highly reputational company with very competitive compensation for all
positions.
Please send in your resume and position/positions you like to apply to my
email address below.
h*******[email protected]
All resumes will be deliver to hiring manager directly. Act fast!
Thanks!
Silicon Engineering Group
Sr. Physical Design Timing Engineer
Timing (STA) Manager
Senior Physical Design Engineer
CAD Manager - Front-End Design and Verification
Sr. CAD Engineer - Place & Route / Physical Design Engineer
Sr. CA... 阅读全帖 |
|
U********7
发帖数: 407 | 7 我刚到组里一个月，partern是一个台湾人，平时感觉还不错，私底下讨论技术的时候
比较随和。但是我发现他在跟director汇报工作的时候经常把我的一些重要的结论拿过
去写在自己的report上，而且不说明，甚至又一次跟我说我给他的testbench没啥大用
处，但是每次写report的时候都把用我的testbench得到的结果说给老板，最过分的是
今天下午的monthly meeting，全组十几个人的会议，他说他来讲我们两个人的工作，
但是竟然只写了自己一个人的，我做的工作什么都不写，我感到有些气愤了，但是我始
终把握的原则还是处理好partership的关系，我不希望两个人最后闹别扭，什么都做不
出来，被一起干掉，但是也不希望这种状况继续下去。大家说说该怎么办？谢谢。 |
|
a******n
发帖数: 55 | 8 Please email: m**[email protected]
Job Description
In this position, the individual will participate in the logic design and
verification of NAND Flash memory products.
Main responsibilities include:
- Development of SystemVerilog TestBench for NAND Flash chips
- Full-chip verification on Flash memory projects with SVTB.
Other responsibilities include:
- Support of SystemVerilog Assertion
- Behavioral modeling in SystemC and C++
- Support of design and verification meth... 阅读全帖 |
|
a*********e
发帖数: 228 | 9 Not actually, Presilicon verification uses a lot of advanced software
techniques now days, but it does not mean it equals software development.
Ultimately, you are not gonna tap out your testbench, you need to develop
your testbench so that it is easier to debug and expose more architecture
issues, It is kind of different with c/c++ software. |
|
n*********h
发帖数: 98 | 10 有意者请站内联系。
The engineer will join automatic random testbench generation team of
Verification Group, Synopsys Inc., in Mountain View, California. This team
leads the development of constraints solver, which generates constrained
random stimuli as input to logic simulator (like VCS from Synopsys).
• You will be responsible for the research, design, development and
debug of current constraints solver, to further improve its performance and
keep industrial leadership.
• You will hav... 阅读全帖 |
|
s***d
发帖数: 15421 | 11 adi我不知道，但是很多模拟的中小公司都是可以互相看的。你设计block 不知道你在
系统里面的环境是很难正确的做出判断的，会出大问题的。很多时候你要拿别人设计好
的bandgap reference，power supply做你自己block的 testbench，所以要是完完全全
独立是不可能的，而且模拟电路那么复杂，光看别人写的设计文档完全没用，设计文档
说得不好听都是放狗屁，至少我自己的设计文档就是放狗屁，干货自己知道就好。 |
|
b**t
发帖数: 102 | 12 (有意请先PM, thanks!)
Principal Logic Design Engineer - SATA Expert
The Processor Division of Broadcom Corporation is well known in the
semiconductor industry for providing super high-performance multi-core
network microprocessors. We are staffing up in critical R&D areas in the
high-rise facility at Highway 101 & Great America Parkway
As a senior Logic Design Engineer you will be responsible for performing
micro-architecture and logic design in the development of I/O devices in
high performance mu... 阅读全帖 |
|
b**t
发帖数: 102 | 13 (有意请PM!)
Job Description
The Processor Division of Broadcom Corporation is well known in the
semiconductor industry for providing super high-performance multi-core
network microprocessors. We are staffing up in critical R&D areas in the
high-rise facility at Highway 101 & Great America Parkway in Santa Clara, CA
.
As a senior system Logic Design Engineer you will be responsible for
performing micro-architecture and logic design in the development of system
logic in high performance multi-threade... 阅读全帖 |
|
h**********l
发帖数: 410 | 14 是吗？除了一篇一作发在一个tier 1 conference （那个领域基本就是conference，几
乎不投journal），还有一篇一作under review。除此之外，我还做了两年半的
undergrad research，三篇一作（不是中文，不过确实是灌水paper，只有一篇还稍微
好一点），也看到了中国top 2的大学的一个组如何做research，也看到了cornell两个
faculty member如何做research，还很快可以看到第三个faculty member以及他的组如
何做research（目前帮他们写了个testbench的app。。。）
在美国第一学期完全摸不到头绪，老师给的advise很多也是错的，后来在郁闷中乱碰了
一下，当然确实lucky work了。当然我在本科申请完学校也换了个课题做毕设，结果老
师不支持（现在导师人真的很好，还是支持我的，也在和我找的合作老师认真交流），
毕设做的一塌糊涂，虽然本科生科研课分数很高（伸了学分就不能作为毕设），毕设只
拿了个良。。。
不过结论是，确实很多research都不实际，好一点的research还能... 阅读全帖 |
|
a******n
发帖数: 55 | 15 In this position, the individual will participate in the logic design and
verification of NAND Flash memory products. Main responsibilities include:
Development of SystemVerilog TestBench for NAND Flash chips. Full-chip
verification on Flash memory projects with SVTB. Other responsibilities
include: Support of SystemVerilog Assertions and behavioral modeling in
SystemC and C++. Support of design and verification methodology enhancements.
This position requires an MS degree or equivalent with 5 o |
|
h*******3
发帖数: 42 | 16 如果你对这个职位感兴趣，请跟我联系。
地点在 San Jose, CA
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Drive and adopt new verification methodologies and flows for efficiency
improvement
Assist with performance analysis and/or architecture
Desi... 阅读全帖 |
|
h*******3
发帖数: 42 | 17 【 以下文字转载自 EE 讨论区 】
发信人: huluwa123 (葫芦娃), 信区: EE
标 题: Open position
发信站: BBS 未名空间站 (Mon Apr 2 19:31:04 2012, 美东)
The position is in San Jose, CA.
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Drive and adopt new verification... 阅读全帖 |
|
h*******3
发帖数: 42 | 18 下面这个职位贴了很久了，应者寥寥啊。有兴趣的话，给我站内信吧。
希望是有经验的。
This position is in San Jose, CA.
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Drive and adopt new verification methodologies and flows for efficiency
improvement
Assist with perfor... 阅读全帖 |
|
h**********l
发帖数: 410 | 19 读phd读到两年半了，虽然research做的其实很顺利，但是觉得原来的project太不主流
了（硬件security），而且感觉没学到什么东西。课也泛泛的在补research需要用的本
科的课，虽然上了不少，都是本科level，而且没有集中在一个领域（我本科电路课上
的是最多的，比如digital，ananog，RF，但是来了美国就没上过电路的课，先按老师
意思上了个solid state physics，然后就开始上关于embedded system，然后关于计算
理论，然后我自己选了一些计算机体系，OS之类的。。。）。现在很囧的要换个合作老
师，要做的和RF和计算机体系比较相关，但是我觉得那个合作老师虽然很热情，但是明
显是用免费的phd资源来try out他的idea，而并没有给我任何承诺。我也很犹豫要不要
继续读phd（人做一个东西久了就成了comfort zone，改变需要时间），还是拿master
走人算了。
另外我觉得我太不愿意冒险了，选课也没有按照master工作的规划来选，而且不知道下
学期一学期才开始找工作，如果没找到怎么办（我如果真的开始找工作，导师不可能不
... 阅读全帖 |
|
b**t
发帖数: 102 | 20 (有意请先PM, thanks!)
Principal Logic Design Engineer - SATA Expert
The Processor Division of Broadcom Corporation is well known in the
semiconductor industry for providing super high-performance multi-core
network microprocessors. We are staffing up in critical R&D areas in the
high-rise facility at Highway 101 & Great America Parkway
As a senior Logic Design Engineer you will be responsible for performing
micro-architecture and logic design in the development of I/O devices in
high performance mu... 阅读全帖 |
|
b**t
发帖数: 102 | 21 (有意请PM!)
Job Description
The Processor Division of Broadcom Corporation is well known in the
semiconductor industry for providing super high-performance multi-core
network microprocessors. We are staffing up in critical R&D areas in the
high-rise facility at Highway 101 & Great America Parkway in Santa Clara, CA
.
As a senior system Logic Design Engineer you will be responsible for
performing micro-architecture and logic design in the development of system
logic in high performance multi-threade... 阅读全帖 |
|
t*****3
发帖数: 81 | 22
就是用面向对象的硬件验证语言（HVL）来构建验证环境（testbench),用matrix
driven methodology来验证逻辑设计。
这两年EE的形式一点都不乐观，LS找到的是什么公司？ |
|
F*D
发帖数: 361 | 23 【 以下文字转载自 JobHunting 讨论区 】
发信人: azurelan (azure), 信区: JobHunting
标 题: Opening : Senior Verification Engineer
发信站: BBS 未名空间站 (Wed Aug 12 17:22:35 2009, 美东)
In this position, the individual will participate in the logic design and
verification of NAND Flash memory products. The individual's main
responsibilities will include development of SystemVerilog TestBench for
NAND Flash chips and full-chip verification on Flash memory projects with
SVTB. The individual's other responsibilities will includ |
|
a******n
发帖数: 55 | 24 In this position, the individual will participate in the logic design and
verification of NAND Flash memory products. Main responsibilities include:
Development of SystemVerilog TestBench for NAND Flash chips. Full-chip
verification on Flash memory projects with SVTB. Other responsibilities
include: Support of SystemVerilog Assertions and behavioral modeling in
SystemC and C++. Support of design and verification methodology enhancements.
This position requires an MS degree or equivalent with 5 o |
|
t***h
发帖数: 25 | 25 华为那边让我过去搭无线接入TESTBENCH，PLAN B就是继续做物探项目。
相比之下我更想接触无线通信的项目啊。我背景就是通信出身。当然
如果能做基带芯片更好。但是这个项目是系统级的项目。之所以要去也是
想以后能再杀回来。还是想尽可能接触不同类型的项目。物探里面的系统
都是低速高温系统，跟通信的高速系统还是有区别的。目前也确实没有好的
PLAN B。 |
|
a******n
发帖数: 55 | 26 In this position, the individual will participate in the logic design and
verification of NAND Flash memory products. Main responsibilities include:
Development of SystemVerilog TestBench for NAND Flash chips. Full-chip
verification on Flash memory projects with SVTB. Other responsibilities
include: Support of SystemVerilog Assertions and behavioral modeling in
SystemC and C++. Support of design and verification methodology enhancements.
This position requires an MS degree or equivalent with 5 o |
|
h*******3
发帖数: 42 | 27 【 以下文字转载自 EE 讨论区 】
发信人: huluwa123 (葫芦娃), 信区: EE
标 题: Open position
发信站: BBS 未名空间站 (Mon Apr 2 19:31:04 2012, 美东)
The position is in San Jose, CA.
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Drive and adopt new verification... 阅读全帖 |
|
i******l
发帖数: 103 | 28 来自主题: SanFrancisco版 - 真的很难过 这个时候就是你最好的学习进步的时候啊！
我当年编程还是大一的时候学的c,后来基本没有碰过，到读研要编图像程序，硬是熬了
个通宵才在第二天把程序交给老师了，当然，当时用的是vb,因为容易嘛。
后来看大家都在打工，于是也去找了个parttime的程序员的事情，老板给了个题目，回
来写了一个晚上，第二天老板说这个小软件写得很好，我很汗哪，这是我第一次用vc,
后来给他们做了1年。
后来一直到现在都做chip就没有用过vbvc了，但是上个工作，老板让搞个memory自动验
证的东西，就搞了几个星期用c,perl,veriloga弄完了，全自动memory的testbench,老
板用过了后那个激动啊，
所以说人都是给逼出来的，现在没有人逼我就只会做circuit了，你现在这么好的机会
当然要硬着头皮上啦，应该恭喜你才对
java
来混，真的迟早是要还 |
|
a******n
发帖数: 55 | 29 In this position, the individual will participate in the logic design and
verification of NAND Flash memory products. Main responsibilities include:
Development of SystemVerilog TestBench for NAND Flash chips. Full-chip
verification on Flash memory projects with SVTB. Other responsibilities
include: Support of SystemVerilog Assertions and behavioral modeling in
SystemC and C++. Support of design and verification methodology enhancements.
This position requires an MS degree or equivalent with 5 o |
|
d**********1
发帖数: 329 | 30 verification Engr
Masters degree (prefer) and 7 - 12 years LCD monitor/TV digital SOC design
verification related experience
Strong background in SOC verification. Expert on SOC system level
verification environment setup and implementation.
Extensive knowledge on System Verliog/OVM, Constraint Driven Verification (
CDV), Coverage Based Verification (CBV), Assertion Based Verification (ABV),
VMM.
Verification plan, testbench and testcases development
Audio/Video sub-system knowledge
Big plus to... 阅读全帖 |
|
t*****e
发帖数: 666 | 31 应该poly的， 其实找工作，有cmos vlsi， vhdl/verilog, computer architeture 就
差不多了。Hardware 现在也需要学一些 c/c++, 因为testbench和behavior model需要
用 面向对象的编程。学校里面争取多点动手的机会，看看跟老师混的时候能不能搞点tape-out，fpga implement的经验。不过hardware的工作确实比较难搞定就是，entry-level的有时
候只有qualcomm，broadcom，marvell，这样大公司有opening。很多小公司不喜欢要刚
毕业的。 网络通信就不知道啥个样子了。 |
|
R*******N
发帖数: 7494 | 32 什么时期的都行, 做testbench用... |
|
m**********g
发帖数: 16 | 33 PLI 调用的效率怎么样---这个不是很明白
使用方便吗-------不难，pli本身建立很简单，调用就和testbench里调函数一样，用$
就可以了 |
|
j***e
发帖数: 486 | 34 在Cadence下,simulator 是 spectre.
testbench 中需要用到random bit generator, vsource 或isource 都行, 要可变
bitrate.
可是cadence 的库里没这模块,我该用什莫办法产生一个呢. 多谢多谢. |
|
R*******N
发帖数: 7494 | 35 FFT, GE, MMT, MP3D之类的哪有下载？OpenMP, Bochs里有testbench的包没？ |
|
t****i
发帖数: 182 | 36 This requires PCB level experience, ATE digital pattern generation, debug,
and ATPG DFT pattern debug experience. Most of the functional tests will
probably be done by the verification team, but you might need to know some
HDL to modify the testbench and re-gen some patterns. |
|
D*e
发帖数: 5 | 37 非牛人.
前端：
1. Architecture design, mainly thinking and high level simulation. I think
this is the most important and fun part once you have gone through several
passes of the whole ASIC design flow.
2. RTL coding and verification by simulation using testbench
3. Assertion based formal verification
4. Logic synthesis using cadence RTL compiler of SNPS DC. Key is to
understand and develop SDC constraint file.
5. Logic equivalency check using Verplex or formality
6. DFT using scan insertio |
|
l*****x
发帖数: 3431 | 38 i don't think so, only use them in testbench file for simulation |
|
a******e
发帖数: 331 | 39 You need to have simulation library .v file with .lib(such as tsmc65lp.v).
After synthesis, you will get .sdf file and you can put
$sdf_annotate(....) in your verilog testbench for simulation.
But I suggest you run STA(PrimeTime) or Formal checking instead as gate
level simulation is time consuming and not so effective in coverage.
have |
|
f*********y
发帖数: 79 | 40 各位大侠 小弟几年5月MS毕业，找到一个verification的工作。以前在国内和这边学的
都是design相关的东西。不知道verification有没有什么好书可以看的？怎么培养验证
思路 写出好的testbench？其实一开始不太想做verification的 后来觉得能学多学点
也很好。
在国内看有人用Vera/System Verilog做验证。这些东西我也是一窍不通，请教如何学
习。
多谢各位 |
|
x**1
发帖数: 892 | 41 formal verification 和 verification 应该totally 两马事情。fv现在根本不需要学
什么东西全都是tool来的。
verification 分的是functional verification还是direct test. direct test 就像
实际应用一样,主要搭系统写testbench写c
function verification看个vmm吧 但这玩意其实也不是这么火爆，花的时间多不一定
出活 |
|
f*****g
发帖数: 112 | 42 方法学方面：
Writing Testbenches: Functional Verification of HDL Models, Second Edition，
Verify工程师人手一本的经典。
Reuse Methodology Manual for System-on-a-Chip Designs：重用设计的思想，芯片
设计的方向。
语言学方面：
具体什么验证语言，取决于公司。
如果什么都不会，就选一个SystemVerilog |
|
T******T
发帖数: 3066 | 43 Not sure for fresh grads, but these are fair game questions.
1) Verilog/VHDL, synthesizable coding style, common mistakes.
2) Design questions : clk div/N(odd), FSM, Async FIFO, Clock domain
crossing techniques, AMBA architecture, setup/hold timing related, maybe
some DSP questions.
3) Verification methodology, from design spec->requirements, testbench setup
, SystemVerilog/Vera/SystemC, assertion, code coverage, fsm coverage,
formal verif, lint, cdc, unit level sim vs system level sim. Random |
|
T******T
发帖数: 3066 | 44 俺帮人以前写的，差不多：
1) Verilog/VHDL, synthesizable coding style, common mistakes.
2) Design questions : clk div/N(odd), FSM, Async FIFO, Clock domain
crossing techniques, AMBA architecture, setup/hold timing related, maybe
some DSP questions.
3) Verification methodology, from design spec->requirements, testbench setup
, SystemVerilog/Vera/SystemC, assertion, code coverage, fsm coverage,
formal verif, lint, cdc, unit level sim vs system level sim. Randomization,
BIST techniques for memory, different p |
|
m*****t
发帖数: 3477 | 45 【 以下文字转载自 Working 讨论区 】
发信人: azurelan (azure), 信区: Working
标 题: Job Opening: Verification Engineer II
发信站: BBS 未名空间站 (Fri Aug 27 12:55:58 2010, 美东)
In this position, the individual will participate in the logic design and
verification of NAND Flash memory products. Main responsibilities include:
Development of SystemVerilog TestBench for NAND Flash chips. Full-chip
verification on Flash memory projects with SVTB. Other responsibilities
include: Support of SystemVerilog Assertions and behavioral |
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T******T
发帖数: 3066 | 46 private sector : mostly verilog, some system-verilog
Public sector/defense/academic: mostly VHDL
Verilog
pro: Much less verbose, more flexible test benching capability.
con: Less strict, more error prone, easier to have synthesis issues.
VHDL
pro: Very strict, less error prone, less headache due to code quality.
con: Much more verbose than verilog (personaly experience is about 15-
20% more lines of code) when describing the same
circuitry, less flexible... 阅读全帖 |
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I***a
发帖数: 704 | 47 systemverilog到底有什么用？
我用verilog写的testbench，
已经有self-checking和random input的功能了.
asic-world上面的一些systemverilog例子，都是要求UUT也用systemverilog写，
但是如果UUT也用systemverilog写，目前根本没有综合软件支持
thanks. |
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h*******y
发帖数: 896 | 48 send me your resume if your background matches this position very well
========================================
Job Posting: Feb 14, 2011
Primary Location: US-TX-Austin-Oak Hill (TX30)
Job: IC Design
Education Level: Bachelor's Degree
Job Type: Recent Graduate
Expectations include:
Verification planning;
Verification test bench infrastructure and environment development and
implementation;
Development of verification testbench components such as drivers, monitors,
response checkers;
Development ... 阅读全帖 |
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h*******y
发帖数: 896 | 49 我上个月发了个找工作的帖子之后，
http://www.mitbbs.com/article_t0/EE/31235757.html
想到还有些东西可以补充一下；另外这期间还收到了一些朋友的留言和email，
其中不少是刚刚毕业新生的一些问题，所以我下面就再后面叽叽歪歪一下analog
的学习和找工作经验，以配合我佛的大无畏精神。
我叽歪的这些东西，有很多其实是我当时找工作和学习过程中想了解，但是苦于
找不到的，现在写下来，希望对大家，特别是还在学校里的学生有帮助和提醒。
当然，这些主要适用于非牛校，非牛人的情况。
==============================================
言归正传，一些关于找工作的一些事情
- 关于猎头，我找工作的时候，收到了很多猎头的电话，并且我很多on-site的面
试机会 都是从猎头那里来的。我感觉猎头对我找工作帮助还是挺大的，猎头和
我们应该是互 惠互利的关系。因为他们如果他们成功帮一个公司招到人的话，
会从公司里拿到佣金。并且，你的工资待遇越高，他们拿到的钱也越多。从这个
角度讲，猎头其实是会尽很大努力来帮忙的。
- ... 阅读全帖 |
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w*******i
发帖数: 108 | 50 【 以下文字转载自 JobHunting 讨论区 】
发信人: huluwa123 (葫芦娃), 信区: JobHunting
标 题: 贴一个非主流的position opening
发信站: BBS 未名空间站 (Mon Mar 26 18:49:41 2012, 美东)
如果你对这个职位感兴趣，请跟我联系。
地点在 San Jose, CA
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Dri... 阅读全帖 |
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