b**y
发帖数: 121 | 1 目前除了IA64支持software managed speculation,
还有什么architecture支持speculation?
PA-RISC/MIPS/Alpha似乎都没有这方面的指令......
哪位牛人给说说? | z*********g
发帖数: 5 | 2 你要说的似乎是predication
PA-RISC/MIPS/Alpha/x86 等依赖硬件speculation, 支持软件predication
当然不必要.
btw, data prefetch指令也是software managed speculation,
一般机器上都有.
【在 b**y 的大作中提到】
: 目前除了IA64支持software managed speculation,
: 还有什么architecture支持speculation?
: PA-RISC/MIPS/Alpha似乎都没有这方面的指令......
: 哪位牛人给说说?
| b**y
发帖数: 121 | 3 Thanks. Here is what I have found after several days search.....
I do mean speculation which is not predication. One example is IA-64's
ld.s/chk.s instruction. With such instructions, software can do speculative
load using ld.s and perform computation on the loaded value. Software uses
chk.s to check if there is exception due to ld.s. If the load cause
exceptions, they are deferred until chk.s checks them and jumps to proper
recovery code (which is part of the software instead of OS). Other mach
【在 z*********g 的大作中提到】
: 你要说的似乎是predication
: PA-RISC/MIPS/Alpha/x86 等依赖硬件speculation, 支持软件predication
: 当然不必要.
: btw, data prefetch指令也是software managed speculation,
: 一般机器上都有.
| z*********g
发帖数: 5 | 4 From what you described, ld.s/chk.s seem a pretty bad design to me. You want
anything that is speculative to be light-weighted. As a result, speculative
loads are usually unbinding - upon an exception, the load is simply squashed.
By adding chk.s for the uncommon cases, you slow the normal cases down ...
load
mechansim.
【在 b**y 的大作中提到】
: Thanks. Here is what I have found after several days search.....
: I do mean speculation which is not predication. One example is IA-64's
: ld.s/chk.s instruction. With such instructions, software can do speculative
: load using ld.s and perform computation on the loaded value. Software uses
: chk.s to check if there is exception due to ld.s. If the load cause
: exceptions, they are deferred until chk.s checks them and jumps to proper
: recovery code (which is part of the software instead of OS). Other mach
| b**y
发帖数: 121 | 5 There are reasons for such speculation scheme. Intel/HP designers are not just
making some fancy stuff in their Itanium/Itanium II processors. In Itanium
processor, control speculation uses ld.s/chk.s to move ld above barriers such
as branches. It's light-weighted and doesn't slow the normal case. If the load
may trigger exception, but finally it turns out that the speculative load is
not in the real path, no exception handling is needed. It's just silently
discarded. If it is in the real path,
【在 z*********g 的大作中提到】
: From what you described, ld.s/chk.s seem a pretty bad design to me. You want
: anything that is speculative to be light-weighted. As a result, speculative
: loads are usually unbinding - upon an exception, the load is simply squashed.
: By adding chk.s for the uncommon cases, you slow the normal cases down ...
:
: load
: mechansim.
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