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EE版 - Re: sigh, 一个搞communication的哥们也要被layoff了
相关主题
ic design or signal processing?请问哪位有好点介绍VHDL的电子书
恳求介绍summer intern in analog design (5+ months from May)求助:verilog的modulus operator
Re: VLSI and Cadence请问做VERILOG/VHDL Simulation 的时候能否调用C/C++ function?
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求助:如何用verilog设计 8-bit squaring ROMBIN->DECIMAL有没有快速实现的算法?
verilog 问题求教请教一个VERILOG的问题
相关话题的讨论汇总
话题: layoff话题: sigh话题: know话题: 哥们
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e****g
发帖数: 2
1
It is impossible as I know. For high-speed communication mixed-signal ICs,
most of the transeivers are analog and custom digtial design.
Now for we can only handle up to 10G by CMOS process and still lots of design
problems. As we all know, it is impossible to handle everything by verilog for
high-speed above 1Ghz.
As I know,it will take a long time to be a nice analog designer.But you are
not end of your carreer. I met several guys with 10-15 years experience. They
are truly mixed-signal, both
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Re: 给推荐两本好书吧(VHDL/Verilog)请教转专业做ic design的MS找intern的经验
相关话题的讨论汇总
话题: layoff话题: sigh话题: know话题: 哥们