h*****u
发帖数: 24 | 1 用VERILOG实现算法的时候，碰到ROUND函数，查了一下，有的是把real data type
truncated to integer data type,但是不能synethesis, 不知道有没有什么其他的解
决办法?多谢 | j***j
发帖数: 324 | 2 you should insert some cores or other functions, and call this function in
your code. Round (for some floating operation ) similar to the division is not a standard operation in
Verilog.
or , do that manually, not hard to write code to implement round.
btw: if you use core generator to generate the function, it is not the most
efficient way for your case, and it will consume a lot of gates. |
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