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发帖数: 17 | 1 Marvell at Colorado is looking for experienced ASIC design and DFT engineers
. Send me resume if you are interested. Positions will be filled shortly.
For DFT engineer:
Responsible for system-on-chip (SoC) test architecture definition, scan
insertion, test IP design, scan pattern generation, verification and ATE
debug
BSEE with 6+ years or MSEE with 4+ years experience in ASIC design
development
Must be familiar with
DFT Methodologies: Scan, Transition-Defect Fault, BIST and JTAG
Synopsys or Men |
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