w*****r
发帖数: 348 | 1 If a design is synthesized into gate level, how to get its power?
For example, in Design Compiler, we use command report_power, however, the
power is different if the toggle rate of signals are different. I am
confused now, how can we claim the power of a design at gate level?
Thanks | m****s
发帖数: 402 | 2 Co-ask. Could anyone kindly give a detailed procedure to follow? In reward,
I will cite your published papers if you agree.
【在 w*****r 的大作中提到】
: If a design is synthesized into gate level, how to get its power?
: For example, in Design Compiler, we use command report_power, however, the
: power is different if the toggle rate of signals are different. I am
: confused now, how can we claim the power of a design at gate level?
: Thanks
| d*****n
发帖数: 235 | 3 一般假定多少百分比的switching rate吧，不太清楚，咱只做过combinational的功率
优化 |
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