r*****s 发帖数: 262 | 1 3阶switch capacitor sigma delta modulator.
输入信号最大频率 22kHz
256倍OSR.sampling frequency 约为11MHz
请问modulator第一级里面的opamp的unity gain frequency最小为多少?
谢谢 |
s***e 发帖数: 35 | 2 the settling time is 1/(2*pi*GBW), where the GBW is gm/C,C is the integrati
ng cap. The integrator needs to settle within half clock cycle, which sets t
he minimum GBW. So it depends on how you size your capacitors. slew rate sho
uld also be considered here.
【在 r*****s 的大作中提到】![](/moin_static193/solenoid/img/up.png) : 3阶switch capacitor sigma delta modulator. : 输入信号最大频率 22kHz : 256倍OSR.sampling frequency 约为11MHz : 请问modulator第一级里面的opamp的unity gain frequency最小为多少? : 谢谢
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r*****s 发帖数: 262 | 3 谢谢回答。
我的问题是
switched capacitor integrator需要settle到1/1000以内?
还是要settle到1/10000以内?或者更精确?
因为我已经给出了half clock cycle的时间长度--》50ns
如果需要settle到1/1000以内,tao=1/(2*pi*f)=50ns/7=7ns
f是integrator的GBW。所以就可以定出opamp的最小带宽
但是如果需要settle到1/10000以内,opamp的最小带宽就是另一个数值了
所以我实际上在问 16bit 3阶modulator的第一级switched capacitor integrator
需要settle到何等精确。
integrati
t
sho
【在 s***e 的大作中提到】![](/moin_static193/solenoid/img/up.png) : the settling time is 1/(2*pi*GBW), where the GBW is gm/C,C is the integrati : ng cap. The integrator needs to settle within half clock cycle, which sets t : he minimum GBW. So it depends on how you size your capacitors. slew rate sho : uld also be considered here.
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r*****s 发帖数: 262 | 4 没人知道吗?
牛人不到这里来逛呀!
【在 r*****s 的大作中提到】![](/moin_static193/solenoid/img/up.png) : 3阶switch capacitor sigma delta modulator. : 输入信号最大频率 22kHz : 256倍OSR.sampling frequency 约为11MHz : 请问modulator第一级里面的opamp的unity gain frequency最小为多少? : 谢谢
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b*********y 发帖数: 830 | |
s***e 发帖数: 35 | 6 Better run some behavioral sim using Matlab
Although your resolution requirement is 96dB, settling to 80dB in half cycle
might be OK if it is linear settling, i.e. not slew rate limited.
【在 r*****s 的大作中提到】![](/moin_static193/solenoid/img/up.png) : 谢谢回答。 : 我的问题是 : switched capacitor integrator需要settle到1/1000以内? : 还是要settle到1/10000以内?或者更精确? : 因为我已经给出了half clock cycle的时间长度--》50ns : 如果需要settle到1/1000以内,tao=1/(2*pi*f)=50ns/7=7ns : f是integrator的GBW。所以就可以定出opamp的最小带宽 : 但是如果需要settle到1/10000以内,opamp的最小带宽就是另一个数值了 : 所以我实际上在问 16bit 3阶modulator的第一级switched capacitor integrator : 需要settle到何等精确。
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e*****e 发帖数: 37 | 7 手算的话:
根据SNR --> 电容最小值(噪声)以及最大的settling 误差
再根据速度要求, 求带宽增 |
r*****s 发帖数: 262 | 8 模拟谁不会呀?
我需要的是settling到何等精度,和其背后的理论解释
【在 b*********y 的大作中提到】![](/moin_static193/solenoid/img/up.png) : 你用simulink模拟一下不就行了
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r*****s 发帖数: 262 | 9 模拟谁都会做,
为什么是80db?
其背后的理论依据是什么?
cycle
【在 s***e 的大作中提到】![](/moin_static193/solenoid/img/up.png) : Better run some behavioral sim using Matlab : Although your resolution requirement is 96dB, settling to 80dB in half cycle : might be OK if it is linear settling, i.e. not slew rate limited.
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e*****9 发帖数: 250 | 10 I think usually settling to 1/2LSB, OTA gain error and gainbandwidth both
contribute to the settling error.
You can look at Prof.Baker's book, mixed signal one, it has detail equations
to calculate that.
Just a fruitful thought:) |
T******n 发帖数: 3180 | 11 人家问的是 sd
equations
【在 e*****9 的大作中提到】![](/moin_static193/solenoid/img/up.png) : I think usually settling to 1/2LSB, OTA gain error and gainbandwidth both : contribute to the settling error. : You can look at Prof.Baker's book, mixed signal one, it has detail equations : to calculate that. : Just a fruitful thought:)
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m********e 发帖数: 585 | 12 It'll depend your resolution requirement. You can use the required
resolution to roughly estimate the SDNR and then settling accuracy.
【在 r*****s 的大作中提到】![](/moin_static193/solenoid/img/up.png) : 谢谢回答。 : 我的问题是 : switched capacitor integrator需要settle到1/1000以内? : 还是要settle到1/10000以内?或者更精确? : 因为我已经给出了half clock cycle的时间长度--》50ns : 如果需要settle到1/1000以内,tao=1/(2*pi*f)=50ns/7=7ns : f是integrator的GBW。所以就可以定出opamp的最小带宽 : 但是如果需要settle到1/10000以内,opamp的最小带宽就是另一个数值了 : 所以我实际上在问 16bit 3阶modulator的第一级switched capacitor integrator : 需要settle到何等精确。
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