A***J
发帖数: 478 | 1 请问ASIC VERIFICATION 职位一般问点啥？
我是FRESH GRAD.有一点ASIC的背景，会C,C++, PERL VERILOG, SYSTEM VERILOG不会，
但知道一点。
对于FRESH的话，问点啥呢。 谢谢 | T******T
发帖数: 3066 | 2 Not sure for fresh grads, but these are fair game questions.
1) Verilog/VHDL, synthesizable coding style, common mistakes.
2) Design questions : clk div/N(odd), FSM, Async FIFO, Clock domain
crossing techniques, AMBA architecture, setup/hold timing related, maybe
some DSP questions.
3) Verification methodology, from design spec->requirements, testbench setup
, SystemVerilog/Vera/SystemC, assertion, code coverage, fsm coverage,
formal verif, lint, cdc, unit level sim vs system level sim. Random | s*****y
发帖数: 1974 | 3 第二部分应该看什么书呢？有专门讲的吗？
我只知道自己做过的一些，不是很全面
setup
,
【在 T******T 的大作中提到】
: Not sure for fresh grads, but these are fair game questions.
: 1) Verilog/VHDL, synthesizable coding style, common mistakes.
: 2) Design questions : clk div/N(odd), FSM, Async FIFO, Clock domain
: crossing techniques, AMBA architecture, setup/hold timing related, maybe
: some DSP questions.
: 3) Verification methodology, from design spec->requirements, testbench setup
: , SystemVerilog/Vera/SystemC, assertion, code coverage, fsm coverage,
: formal verif, lint, cdc, unit level sim vs system level sim. Random
| T******T
发帖数: 3066 | 4 I don't know of 1 single book that covers them all, but you can pretty much
find, learn about these topics by just Googling them. At least for fifo,
cdc design, there are lots of whitepapers.
【在 s*****y 的大作中提到】
: 第二部分应该看什么书呢？有专门讲的吗？
: 我只知道自己做过的一些，不是很全面
:
: setup
: ,
| d****o
发帖数: 1112 | 5 strongly suggest to read some books....googling around may confuse you.
much
【在 T******T 的大作中提到】
: I don't know of 1 single book that covers them all, but you can pretty much
: find, learn about these topics by just Googling them. At least for fifo,
: cdc design, there are lots of whitepapers.
| T******T
发帖数: 3066 | 6 ok, fine, then get "HDL chip design" book as a starter
【在 d****o 的大作中提到】
: strongly suggest to read some books....googling around may confuse you.
:
: much
| s*****y
发帖数: 1974 | 7 Thanks，就是一直感觉在第二点上没有系统训练过
【在 T******T 的大作中提到】
: ok, fine, then get "HDL chip design" book as a starter
| T******T
发帖数: 3066 | 8 这个比较难在interview 前临时抱佛脚，如果有时间可以自己写几个小design,在面试
前用
modelsim练练手。 关于timing 的问题要坐下来读书，想想，RTL sim 对这个没用。
【在 s*****y 的大作中提到】
: Thanks，就是一直感觉在第二点上没有系统训练过
| A***J
发帖数: 478 | 9 will be interviewed next Monday. bless thank you TroubleT | T******T
发帖数: 3066 | |
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