f*********r
发帖数: 674 | 1 Senior VLSI/Physical Design Engineer
Submit ResumeSilicon Valley
This position requires an understanding of RTL to GDS flows, CMOS device
operation and advanced layout rules.
Responsibilities:
* Ownership of design floor planning, synthesis, DFT, place and route,
clock and power distribution, static timing analysis, signal integrity
analysis, physical verification.
* Use circuit design skills to verify clock and power implementation.
* Contribute to developing physical design methodo | s*******p
发帖数: 156 | 2 你们那里老印把持中层吗，工作强度怎么样？
GDS
【在 f*********r 的大作中提到】
: Senior VLSI/Physical Design Engineer
: Submit ResumeSilicon Valley
: This position requires an understanding of RTL to GDS flows, CMOS device
: operation and advanced layout rules.
: Responsibilities:
: * Ownership of design floor planning, synthesis, DFT, place and route,
: clock and power distribution, static timing analysis, signal integrity
: analysis, physical verification.
: * Use circuit design skills to verify clock and power implementation.
: * Contribute to developing physical design methodo
| f*********r
发帖数: 674 | | f*********r
发帖数: 674 | 4 division经理是巴基斯坦人, architect是白人, manager大部分都是白人... 干活的不
是老印就是老中. 很少有白人就是了... | l****r
发帖数: 97 | 5 这是在老的netlogic部门，还是新买来的部门？谢谢。
【在 f*********r 的大作中提到】
: division经理是巴基斯坦人, architect是白人, manager大部分都是白人... 干活的不
: 是老印就是老中. 很少有白人就是了...
| f*********r
发帖数: 674 | |
|
