I***a
发帖数: 704 | 1 In Design Compiler, 我用write_sdf命令得到的.sdf文件back-annotate到综合后的
verilog netlist总是有这个问题:
Instance '/FFT8inputs/\Regs_4/Q_reg[20] ' does not have a generic named 'tpd
_clk_q_posedge'.
tpd_clk_q_posedge, tpd_clk_qbar_posedge, tsetup_d_clk_posedge_posedge,
tsetup_d_clk_negedge_posedge, thold_d_clk_posedge_posedge, thold_d_clk_
negedge_posedge,
这6个generic参数说是对应的DFF cell里没有:
entity DFF_E is
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.156 ns, 0.
111 ns);
tpd_CLK_QBAR : VitalDelayType01 := (0.078 ns, 0.
110 ns);
tsetup_D_CLK : VitalDelayType := 0.189 ns;
thold_D_CLK : VitalDelayType := -0.013 ns;
tpw_CLK_posedge : VitalDelayType := 1.063 ns;
tpw_CLK_negedge : VitalDelayType := 1.063 ns;
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.
000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.
000 ns));
port(
Q : out STD_ULOGIC;
QBAR : out STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC); |
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