I***a 发帖数: 704 | 1 systemverilog到底有什么用?
我用verilog写的testbench,
已经有self-checking和random input的功能了.
asic-world上面的一些systemverilog例子,都是要求UUT也用systemverilog写,
但是如果UUT也用systemverilog写,目前根本没有综合软件支持
thanks. |
S******s 发帖数: 5376 | 2 systemverilog can be synthesizable......
【在 I***a 的大作中提到】![](/moin_static193/solenoid/img/up.png) : systemverilog到底有什么用? : 我用verilog写的testbench, : 已经有self-checking和random input的功能了. : asic-world上面的一些systemverilog例子,都是要求UUT也用systemverilog写, : 但是如果UUT也用systemverilog写,目前根本没有综合软件支持 : thanks.
|
I***a 发帖数: 704 | 3 what software can synthesize systemverilog?
【在 S******s 的大作中提到】![](/moin_static193/solenoid/img/up.png) : systemverilog can be synthesizable......
|
o****m 发帖数: 633 | 4 system verilog is a super set of verilog, used for effective verification.
Then when it is read in EDA tools, all the verification infomation is
discarded, hence only verilog part is kept and synthesized.
【在 I***a 的大作中提到】![](/moin_static193/solenoid/img/up.png) : what software can synthesize systemverilog?
|
I***a 发帖数: 704 | 5 胡说
【在 o****m 的大作中提到】![](/moin_static193/solenoid/img/up.png) : system verilog is a super set of verilog, used for effective verification. : Then when it is read in EDA tools, all the verification infomation is : discarded, hence only verilog part is kept and synthesized.
|