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EE版 - 南加招聘FPGA/ASIC Design Engineer,站内信箱联系
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1 (共1页)
i******y
发帖数: 48
1
FPGA/ASIC Design Engineer
Location: Southern California, CA
The FPGA/ASIC Design Engineer is responsible for the design of control, and
manufacturing chip systems utilizing advance high density FPGA products and
transition to ASIC/SoC design. This includes all areas of digital design of
FPGA/ASIC development including chip architecture, RTL, implementation, RTL
synthesis, validation, and lab bring-up and characterization. The Engineer
works with advanced development teams on developing next generation PCU
technology.
Requirements:
· Bachelor of Electronics Engineering (4 years tertiary);
Master of Engineering (2 years post grad) or PhD preferred
· 3-5 years of direct FPGA/ASIC design experience
· Experience in Digital ASIC and FPGA
· Familiar with both Verilog and VHDL programming
· Expertise with FPGA/ASIC design methodologies including
Verilog HDL, timing Constraints, Timing Closure, synthesis, and Verification
· Understanding synchronous and asynchronous circuit design
· Knowledge of Xilinx FPGA implementation flow and experience
of ISE design tools (including coregen and chipscope)
· Knowledgeable in advanced complex FPGA products
· Experience of ModelSim simulation tools
· Knowledge of Perl and Matlab, a plus.
w*********3
发帖数: 70
2
不知道要不要本科生,现在在读大三,希望能先找个inten或者co-op
1 (共1页)
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