f*********9
发帖数: 5 | 1 本人EE-VLSI master。主要想找Asic Design, Design Verification, Physical
Design.最近不知道是market不好，还是我简历有很大问题，投出去的简历没有任何回
应。求高
人指点，非常感谢。
简历如下：
============================================================================
=========
TECHNICAL SKILLS
Programming Language: Verilog, VHDL, SystemVerilog, C, C++, Perl
Applications: Design Compiler, PrimeTime, Encounter, NCSim, Virtuoso,
Modelsim
WORKING EXPERIENCE
Course Mentor (TA) for Diagnosis and Design of Reliable Digital Systems
Fall 2014
Developed homework and project, and held office hours to solve students's
confusion in the course
ACADEMIC PROJECTS
DDR2 Memory Controller (Verilog, Design Compiler, PrimeTime, Encounter)
Fall 2014
Completed ASIC flow for Memory Controller from RTL to physical specification
(GDSII)
Verified the function for RTL, and checked timing (STA) and function for the
synthesized netlist
Implemented floor plan, place and route, clock tree synthesis, setup/hold
check and optimization
Router Verification Using Constrained Random Process (SystemVerilog,
Modelsim)Fall 2014
Created verification plans and implemented test code, functional coverage
based on specification
Built the verification environment from basic components, including packet,
driver, scoreboard, etc
Implemented assertion (SVA) to verify design specification, such as the
interfaces and routing
Tomasulo Dynamically Scheduled Processor (VHDL, Modelsim, Xilinx ISE, FPGA)
Summer 2014
Designed an out of order processor based on Tomasulo with speculation and
explicit register renaming
Implemented modules including branch prediction buffer, register alias Table
, re-order buffer, etc
Verified the design using different instruction streams
Full Custom General Purpose Microprocessor (Perl, Cadence Virtuoso)
Spring 2014
Designed a multi-cycle CPU which supports a subset of MIPS with 6T SRAM as
register file
Wrote Perl to read instructions and work as control unit, and designed
schematic and layout for data path
Generated golden results and verified functionality automatically using Perl
scripting
Optimized the design using logic efforts, clock gating, etc and won top
designers for performance
Network on Chip with Forward Error Correction (SystemVerilog)
Spring 2014
Built a package based asynchronous network on chip consisting of 8 nodes
using hybrid topology
Implemented router, arbiter, and encoder/decoder with Hamming error
correction
Designed testbench to insert noise, check the package match, and generate
communication scenarios
ATPG Tool Design for Combinational Circuit with Stuck at Faults (C language)
Fall 2013
Implemented an ATPG tool consisting of pre-processor, pattern generator and
fault simulator
Coded the pre-processor to read circuits input file, form the data structure
, and generate fault list
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复制粘贴的文本，粘过来排版有些混乱。
另如果有内推之类的，希望能联系我，万分感谢。 | e***y
发帖数: 4307 | | n*****n
发帖数: 5277 | | e*******s
发帖数: 147 | 4 没有实习是硬伤，而且现在VLSI真心难找，身边有人有实习，人也在湾区，找了很久也
找不到最后转软了 | f*********9
发帖数: 5 | 5
是呢 挺难找了 一学期不如一学期啊。简历有什么建议么？多谢
【在 e***y 的大作中提到】
: 现在vlsi工作很不好找了。。
| f*********9
发帖数: 5 | 6
嗯 打算六月份一毕业就搬过去。去那边的话有多大的优势呢？
【在 n*****n 的大作中提到】
: 建议杀到弯曲去，不在弯曲找vlsi的工作很难
| f*********9
发帖数: 5 | 7
嗯，是呀。本来这学期有个NVIDIA实习，但是学校不给CPT，最终也没去成。也打算毕
业了可以先找个实习干一干。不知道毕业生找实习是不是很难？
【在 e*******s 的大作中提到】
: 没有实习是硬伤，而且现在VLSI真心难找，身边有人有实习，人也在湾区，找了很久也
: 找不到最后转软了
| n*****n
发帖数: 5277 | 8 那边面试应该好拿多了，另外多找同学帮忙推荐，据说那边vlsi的工作还是不少
【在 f*********9 的大作中提到】
:
: 嗯，是呀。本来这学期有个NVIDIA实习，但是学校不给CPT，最终也没去成。也打算毕
: 业了可以先找个实习干一干。不知道毕业生找实习是不是很难？
| f*********9
发帖数: 5 | 9 好多，多谢了
【在 n*****n 的大作中提到】
: 那边面试应该好拿多了，另外多找同学帮忙推荐，据说那边vlsi的工作还是不少
| r*******c
发帖数: 125 | 10 毕业了就不好找intern了，很多公司要求毕业生只能full time
实习是多宝贵的机会啊，学校为啥不给CPT?
【在 f*********9 的大作中提到】
: 好多，多谢了
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