t******l
发帖数: 77 | 1 ntel Folsom validation team has multiple opens.
1. SW/FW developer: senior and junior position; Good knowledge of C/C++,
Python. prefer having validation experience and understanding the low level
HW/SW interaction (such as driver)
2. System validation engineer: senior and junior position: system level
validation in pre-si (SLE/FPGA etc) and post-si. Need to understand the
computer arch, validation, C/C++, debug SW and HW etc. prefer experiencing
RTL, board, scope/LA etc.
https://intel.taleo.net/careersection/10003/jobdetail.ftl?job=772760
3. PM (program manager): senior position. Need to experience project
management, understand PLC (product life cycle), drive cross sites and
cross team operation/tasks, demonstrate the leadership and ownership.
4. PHY technical lead (validation): senior position. Need to experience high
speed IO PHY design or debug. Drive the validation requirement (DFV) into
silicon for the fast TTM, drive the validation and debug, oversee the long
term PHY validation strategy.
Please send your questions and resume to [email protected]
/* */ and mention the
position you are interested.
Good luck! | t******l
发帖数: 77 | 2 ntel Folsom validation team has multiple opens.
1. SW/FW developer: senior and junior position; Good knowledge of C/C++,
Python. prefer having validation experience and understanding the low level
HW/SW interaction (such as driver)
2. System validation engineer: senior and junior position: system level
validation in pre-si (SLE/FPGA etc) and post-si. Need to understand the
computer arch, validation, C/C++, debug SW and HW etc. prefer experiencing
RTL, board, scope/LA etc.
https://intel.taleo.net/careersection/10003/jobdetail.ftl?job=7
3. PM (program manager): senior position. Need to experience project
management, understand PLC (product life cycle), drive cross sites and
cross team operation/tasks, demonstrate the leadership and ownership.
4. PHY technical lead (validation): senior position. Need to experience high
speed IO PHY design or debug. Drive the validation requirement (DFV) into
silicon for the fast TTM, drive the validation and debug, oversee the long
term PHY validation strategy.
Please send your questions and resume to [email protected]/* */ and mention the
position you are interested.
Good luck! | t******l
发帖数: 77 | 3 Intel Folsom validation team has multiple opens.
1. SW/FW developer: senior and junior position; Good knowledge of C/C++,
Python. prefer having validation experience and understanding the low level
HW/SW interaction (such as driver)
2. System validation engineer: senior and junior position: system level
validation in pre-si (SLE/FPGA etc) and post-si. Need to understand the
computer arch, validation, C/C++, debug SW and HW etc. prefer experiencing
RTL, board, scope/LA etc.
3. PHY technical lead (validation): senior position. Need to experience high
speed IO PHY design or debug. Drive the validation requirement (DFV) into
silicon for the fast TTM, drive the validation and debug, oversee the long
term PHY validation strategy.
Please send your questions and resume to [email protected]/* */ and mention the
position you are interested.
Good luck! |
|
