a*****9
发帖数: 790 | 1 【 以下文字转载自 BayAreaJobSeekers 俱乐部 】
发信人: amy2009 (benben), 信区: BayAreaJobSeekers
标 题: multiple openings in ASIC design(Santa Clara)
发信站: BBS 未名空间站 (Sat Feb 12 22:57:21 2011, 美东)
DFT:
Know details about the tap controller, scan, ATPG, ATE test, etc
good understanding and hands on experience in certain DFT field.
quick, have the knowledge of DFT, good team player
Digital Design:
RTL coding, micro-architecture, Verilog,
quick hands, easy to get along with, good team player.
it's better to know something related with ARM cpu, SoC, or
synthesis, sta, but it’s not required.
Implementation Engineer:
Synthesis, Timing constraint, STA, must have
Low power flow, UPF/CPF, good to have.
Back-end, place & route, good to have.
FPGA experience, good to have. | a*****9
发帖数: 790 | 2 if interested, pls send a message to LZ. Thxs.
【在 a*****9 的大作中提到】
: 【 以下文字转载自 BayAreaJobSeekers 俱乐部 】
: 发信人: amy2009 (benben), 信区: BayAreaJobSeekers
: 标 题: multiple openings in ASIC design(Santa Clara)
: 发信站: BBS 未名空间站 (Sat Feb 12 22:57:21 2011, 美东)
: DFT:
: Know details about the tap controller, scan, ATPG, ATE test, etc
: good understanding and hands on experience in certain DFT field.
: quick, have the knowledge of DFT, good team player
: Digital Design:
: RTL coding, micro-architecture, Verilog,
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