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发帖数: 42 | 1 【 以下文字转载自 EE 讨论区 】
发信人: huluwa123 (葫芦娃), 信区: EE
标 题: Open position
发信站: BBS 未名空间站 (Mon Apr 2 19:31:04 2012, 美东)
The position is in San Jose, CA.
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Drive and adopt new verification methodologies and flows for efficiency
improvement
Assist with performance analysis and/or architecture
Desired skills and experiences:
Minimum 5 years or equivalent experiences in design and verification
Strong experience in verification flow and DV methodologies
Hands on experience in video codec and video processing
Familiar with MPEG, AVC/H.264, VC-1 and VP8 video standards
Strong C/C++, Verilog programming and scripting language capability
Highly motivated and be able to work both independently and as a team
member
Experience in SystemVerilog, UVM/OVM/VMM is a strong plus
Working knowledge of processor architecture a plus
MS in EE, CS or CE |
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