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JobHunting版 - Senior ASIC Design Verification engineer openning
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l**t
发帖数: 10440
1
【 以下文字转载自 SanFrancisco 讨论区 】
发信人: lint (half life), 信区: SanFrancisco
标 题: Re: 【JOBS广告】04.01 -- 04.30
发信站: BBS 未名空间站 (Sat Apr 7 00:50:39 2012, 美东)
A big semiconductor company(Bay area, CA) is hiring Senior Design
Verification Engineer
Must:
EE MS, at least 2 years+
System Verilog/OVM or VMM
Plus:
DMA
PCIE
Please email your questions/resume to l******[email protected], thanks!
(We dont need new graduates, thanks)
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