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发帖数: 692 | 1 【 以下文字转载自 JobHunting 讨论区 】
发信人: shadingyu (fish), 信区: JobHunting
标 题: 【工作机会】SerDes System Architect - Portland
发信站: BBS 未名空间站 (Mon Jul 8 17:49:01 2019, 美东)
Experience:
• MSEE or PHD with minimum of 7+ years of experience in architecting
high speed I/O system and FPGA or ASIC design
• Thorough knowledge in communication and digital signal processing,
in particular equalization, adaptation algorithms, clock data recovery and
link noise budgeting and analysis.
• Knowledge & hands-on experience with one or more of the following IO
protocols: PCIe, SATA, USB, SGMII, Interlaken, 10G Base–KR, CEI, FC, XAUI,
XPON, DDR3/4, LPDDR3/4, Intel PIPE 3.0 and above.
• A track record in delivering high volume commercial products from
architecture definition to post-silicon product qualification, & working
knowledge in industry best practices
• Previous experience in TSMC/UMC’s 40nm process or more advanced
node, PI/SI &
channel analysis, and IP’s SoC/system integration & validation flow is a
strong plus.
• Past experience in supporting deal acquisition and external customer
engagement is a must.
Skill:
• Strong fundamental in circuit theory, design and layout
• Knowledge in digital signal processing, control theory, system
behavior modeling with matlab/IBIS-AMI or Verilog/Verilog-A, and IO’s
training algorithm is a strong plus
• Creative design and problem solving ability delivering the highest
level result across power, performance and area
• Experience in Cadence, HSPICE design flow, static timing analysis,
and analog-mixed signal behavior modeling and verification
• Strong communication and presentation skills. Ability to work
independently with local and international teams under different time zone
and language background.
• Ability to work across all functional levels. Highly disciplined and
self-motivated. Able to support occasional domestic or international travel
per business requirement.
• Fluent in both Chinese & English is a strong plus
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