S*******s
发帖数: 1 | 1 Open Source RISC-V Postdoc Position
University of Washington, CS & EE Department
Location: Seattle, CA
Postdoctoral positions are available immediately to join the productive
Bespoke Silicon Group (BSG) at the University of Washington http://darksilicon.net ).
BSG Leader Professor Michael Taylor received his PhD at MIT and was lead
architect of the 16-core MIT Raw tiled multicore processor, one of the
earliest multicore processors, which predates Intel’s multicore chips. He
co-authored the earliest published research on dark silicon. More recently,
Taylor wrote the first academic paper on Bitcoin mining chips.
In last two years, our team have published paper in ISCA’16, ASPLOS’17,
Hotchips’17 and IEEE MICRO’17. Our research focuses on manycore (kilo-core
) and ASIC Could. We proposed neural network ASIC Clouds before Google
announced their TPU.
Our team is tapeout driven. We made 3 tapeouts in 2017, including the 511-
core RISC-V compatible Celerity chip, in TSMC 16nm technology. It executes
500 Billion RISC-V instructions per second, using 25 mm^2 of silicon, and is
the most powerful RISC-V chip ever created.
-----Job Description-----
The postdoc position is to support the 4-year open source microprocessor
project, which will tapeout a multi-core RISC-V 64G processor with open
source EDA tools.
A PhD in CS or EE disciplines is required. Previous training and experiences
in the following research areas are prefered:
Microprocessor tapeout experience is a huge plus.
Microprocessor pipeline design, verification and optimization experience.
On-chip memory system (cache, atomic memory operation) design & verification
experience.
Strong microprocessor verification experience (verification environment
building, test generation, coverage analysis).
Strong physical design experience (STA, P&R, CTS, LVS, DRC, Formality, SI
etc).
Open source project experience, clean SystemVerilog coding style.
Top tier publications.
Please send CV, personal statement to Shaolin Xie ([email protected]). |
|
