s******n
发帖数: 44 | 1 We have a few opennings for ASIC design and verfication positions.
Openning 1: Synthesis, CDC, LEC for our different IPs;
Openning 2: ASIC verification engineer, system verilog experience is must;
Openning 3: Digital ASIC design engineer, intermediate-level.
Openning 4: SSD (Solid State Disk) Field Applications Engineer. Read Channel
experience is ideal.
Please feel free to send me email if you are interested.
Thanks, | l**t
发帖数: 10440 | 2 太明显了
Channel
【在 s******n 的大作中提到】
: We have a few opennings for ASIC design and verfication positions.
: Openning 1: Synthesis, CDC, LEC for our different IPs;
: Openning 2: ASIC verification engineer, system verilog experience is must;
: Openning 3: Digital ASIC design engineer, intermediate-level.
: Openning 4: SSD (Solid State Disk) Field Applications Engineer. Read Channel
: experience is ideal.
: Please feel free to send me email if you are interested.
: Thanks,
| i*o
发帖数: 149 | | x***n
发帖数: 464 | 4 请查站内信。谢谢！
must;
Channel
【在 s******n 的大作中提到】
: We have a few opennings for ASIC design and verfication positions.
: Openning 1: Synthesis, CDC, LEC for our different IPs;
: Openning 2: ASIC verification engineer, system verilog experience is must;
: Openning 3: Digital ASIC design engineer, intermediate-level.
: Openning 4: SSD (Solid State Disk) Field Applications Engineer. Read Channel
: experience is ideal.
: Please feel free to send me email if you are interested.
: Thanks,
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