a******n
发帖数: 55 | 1 This individual will work on next generation 3D flash memory chip design.
This individual will contribute from RTL to GDS on block level designs.
Specific tasks will include but not limiting the following:
- design floor planning, place and route
- CTS (Clock Tree Synthesis) and timing analysis
- physical design verification and debug
- ECO (Engineering Change Order) on existing database
Job Requirements:
- MSEE or MSCS with 3+ year experience of digital physical design.
- Experience with RTL 2 GDSII concepts and flows.
- Requires good programming/scripting skills in SKILL, TCL, perl or
Python.
- STA (Static Timing Analysis) experience
- Experience with industry standard toolsets from Cadence (SOC) or
Synopsys (ICC).
- Experience of physical verification such as DRC, LVS and XOR.
- Excellent communication skills, both written and verbal.
- Ability to work in a team environment | m*********s
发帖数: 354 | 2 full time, part time, freelance? | a******n
发帖数: 55 | 3 full time, SNDK
【在 m*********s 的大作中提到】
: full time, part time, freelance?
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