B*******e
发帖数: 3882 | 1 "Backgrounds are displayed in Web layout view only and aren't designed for p
rinting. Watermarks are intended for printed documents."
To work around this, I know two options here:
1. Make sure ur "View" is at "Normal", then On the Format menu, point to Bac
kground, and then click Printed Watermark, choose a pic. But the pic is wash
ed out to some extend even if u uncheck "washout"
2. insert a pic, and rightclick the pic, choose "Format pic", then layout, u
will c |
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j*****d
发帖数: 88 | 2 这个坛子太冷清，贴个笑话。
A tourist walked into a pet shop and was looking at the animals on
display.
While he was there, another customer walked in and said to the
shopkeeper, "
I'll have an AutoCAD monkey please." The shopkeeper nodded, went over to
a cage at the side of the shop and took out a monkey. He fitted a collar
and leash, handed it to the customer, saying, "That'll be $5000." The
customer paid and walked out with his monkey.
Startled, the tourist went over to the shopkeeper and said, "That was a... 阅读全帖 |
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c***3
发帖数: 251 | 3 We are pleased to announce the first beta release of the Mosaic plugin. This
is the first of a suite of plugins under development for annotating,
analyzing and visualizing networks with Gene Ontology terms. Mosaic uses
all three branches of GO to:
* Partition into subnetworks based on Biological Process terms
* Layout each subnetwork using a cellular template based on Cellular
Component terms
* Color nodes based on Molecular Function terms
Start with a network having any standard gene identifie... 阅读全帖 |
|
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h***z
发帖数: 233 | 5 a) Adding a new constructor (not default constructor) is SAFE. Memory
layout of the class and existing methods are not affected.
b) Adding a data member is NOT safe. Memory layout of the class is changed.
A new member variable changes the size of the class, as well as offsets of
the existing member variables (depending on where the new member variable
is added). The old libraries will all be assuming the old size and offsets
of the class.
c) Changing destructor to virtual is NOT safe, since |
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r*******n
发帖数: 70 | 6 Schematic：Cadence Virtuoso Schematic Composer
Layout: Cadence Virtuoso Layout Editor
Simulator: HSPICE, spectre...
以上是最最基本的,建议还是选一门课 |
|
r****n
发帖数: 918 | 7 go for RF if you can.
Digital is a very broad area. It involves many layers. I believe top layer
will still be kept in us for a long time.
Good analog circuit design need to understand layout, layout need to
understand device fab, fab need to under physics....analog is easy to do
application, difficult to design. |
|
f*****0
发帖数: 489 | 8 opa627 is a high-speed voltage feedback amp. As such, it is very easy to get
into oscillation if you aren't careful with its layout, and power supply
decoupling.
it doesn't have high current capability so short of mis-wiring, your cuircit
is almost surely oscillating. the chip is likely done.
go through the datasheet and pay particular attention to decoupling and
layout and get a scope to see the output wave form. |
|
x****g
发帖数: 2000 | 9 图片来自razavi Figure 11.14(b).
小弟想问一下像图书的Q2在cadence schematic里面应该如何去接？
用的是nwell的CMOS技术。
Q1由于b,c是接在一起的，容易实现。
Q2的b,c连接到不同的地方，这样的接法在layout里面可以直接实现，但在schematic里
面该怎么接我就没主意了，Q2的c跟pmos4的哪个端口都不对应，如果不接c的话，我试
了一下所有电流都从基极流走了，这样Q2的电流放大系数就成了0了，电路起不到作用。
请牛牛们指点，
谢谢
ps:
不好意思，我没说清楚
我想问的是，我现在要用pmos实现它，我用的ami0.6不支持bjt的。
我没有bjt，只能化个示意图，
Q1那个bjt我可以把pmos的s&d连一起作为e，bulk做为b，这么接出来，
Q2的那个bjt在layout里面也可以很简单的用pmos实现，但schematic里面怎么弄呀？
谢谢 |
|
f********o
发帖数: 2181 | 10 在做一个LC-OSC
发现layout以后提取的网表怎么也不起振
我把extraction的设置设成只提取电路元件不提寄生RC
然后手动把寄生二极管删了也跑不起来
因为layout后出现几千个transistor并联
手动查很麻烦, 不过LVS是正常的
这样extracted netlist应该和schematic一样吧, 因为没有任何寄生元件
是不是并联的transistor和在schematic里面设置成finger有很大差别?
从schematic的仿真来看tuning range蛮大的
不知道这些变化是不是有问题?
实在想不明白, 请高手指教
多谢 |
|
x***y
发帖数: 830 | 11
ADS is not good for multilayer sim. HFSS is better. I believe it can
interface
with cadence
IE3D can also do the job but drawing layout in IE3D is a pain in the ass..
You can draw the layout in cadence and export GDS file to IE3D |
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n***d
发帖数: 647 | 12 如果以后的人对设计有新的改进，当然他们是第一作者。
但是该同学做的是Layout和Test。连很多部分的layout都是从我的第一版本copy过来的。 |
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c******s
发帖数: 197 | 13 orcad只是schematic，或许你说的是layout plus，好像现在layout都不卖了，cadence
只推allegro，据说是最牛x 的PCB 软件之一，我们这里都设计低速的电路，所以没有
特别的要求 |
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a******e
发帖数: 331 | 14 你有Synopsys的Solvnet户头吗？有的话可以去以下下载
http://www.synopsys.com/Community/UniversityProgram/Pages/defau
90nm Generic Library Content
Technology Kit
The Technology Kit includes a databook and user guide, symbols, .lib,
Verilog and VHDL simulation models, DRC and LVS decks, HSPICE netlists,
extracted C/RC netlists, GDSII layout views, LEF files, generic SPICE models
, fram views, layout views and runset files.
Digital Standard Cell Library
The Digital Standard Cell Library consists of 340 cells to optimi... 阅读全帖 |
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T******T
发帖数: 3066 | 15 Yeab, rules and constraints are given as the 1st pass procedure. The
prelim layout is reviewed, extracted into sigrity and ansoft simulation
suites and carefully analyzed for 2nd pass. That's when we sit with the
PCB layout guys to start tweaking things. Many HW guys don't really
believe in the tools and still like to use rule of thumb, and most of the
time, it works out fine for them, but I still prefer a more methodical
process.
your
carefully. |
|
e****d
发帖数: 5 | 16 Job Title: Senior ASIC Design Engineer/ Group Leader
Brief description of job duties:
路 Maintain and upgrade IC CAD tools such as (Cadence/Xlinix/Calibre
)
路 Perform IC Layout, both top level and analog layout
路 Organize design review meetings and get ready for tape out
submission
路 Interface with foundries and vendors during the design,
simulation, integration and testing of ASIC ICs
路 Provide leadership within the ASIC group and manage daily
activities |
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h*******y
发帖数: 896 | 17 If your background matches this position, please send me your resume
(email needed).
========================
Analog and Mixed Signal IC Design Engineer
Job Posting: Jan 24, 2011
Primary Location: US-TX-Austin-Oak Hill (TX30)
Job: Analog and Mixed Signal
Education Level: Bachelor's Degree
Job Type: Experienced
Scope of Responsibilities/Expectations:
Design of analog and mixed signal circuits in advanced CMOS technologies for
automotive and industrial & multi-market applications; including defini... 阅读全帖 |
|
V******B
发帖数: 3940 | 18 你把schematic的图画出来，然后布线好
就把PCB layout的文件发给制版商就可以了，等一到两个星期就可以收到，收费是看板
子的大小，几
层板
google PCB layout 然后查一下review，挑一个review不错的，然后就上那个网站，
upload 文
件，付钱。给网站的representitve打电话，问一下情况 |
|
h*******y
发帖数: 896 | 19 我把自己这两个多月找analog电路设计的工作的经历写下来，希望对大家有
帮助。
先说说我面试的公司，我在7月初开始修改简历，然后把简历放到网上，期间收
到了这些公司的面试，AMD, NXP, Cirrus Logic, Intel, Intrinsix, Micrel,
Zarlink，3家小公司M/R/S.其中只有一个公司把我拒了，拿到了其他全部公司
的offer。另外拿到了TI和Qualcomm的on-site的面试机会，不过没时间去了，
就婉拒了。另外Atmel完成了电话面试之后说会给我消息，不过我已经没法等
了。还有一个比较奇怪的Analog Device的面试，他们没有工作位置，但是一
个部门的经理对我做的项目感兴趣，给我电话聊了一下。
下面我讲讲面试的一些经历，但愿对你们找工作有帮助和提醒。
==============================================================
NXP
- 这个工作位置是由猎头介绍的。
- 我去面试之前这个猎头发了一个面试的schedule给我，里面列出来了每个面
试官的名字，并且还有他们会问的侧... 阅读全帖 |
|
h*******y
发帖数: 896 | 20 我把自己这两个多月找analog电路设计的工作的经历写下来，希望对大家有
帮助。
先说说我面试的公司，我在7月初开始修改简历，然后把简历放到网上，期间收
到了这些公司的面试，AMD, NXP, Cirrus Logic, Intel, Intrinsix, Micrel,
Zarlink，3家小公司M/R/S.其中有一个公司把我拒了，拿到了其他全部公司
的offer。另外拿到了TI和Qualcomm的on-site的面试机会，不过没时间去了，
就婉拒了。另外Atmel完成了电话面试之后说会给我消息，不过我已经没法等
了。还有一个比较奇怪的Analog Device的面试，他们没有工作位置，但是一
个部门的经理对我做的项目感兴趣，给我电话聊了一下。
下面我讲讲面试的一些经历，但愿对你们找工作有帮助和提醒。
==============================================================
NXP
- 这个工作位置是由猎头介绍的。
- 我去面试之前这个猎头发了一个面试的schedule给我，里面列出来了每个面
试官的名字，并且还有他们会问的侧重... 阅读全帖 |
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s******7
发帖数: 1091 | 21 I can send your resume to hiring manager directly if background matches.
Sponsor h1b
experience in Candence or IC station layout tool
Develop new cell generator for designers( DRC Die/Frame)
Layout of new devices
Implement new versions of CAD software
Interface to IT for all kinds of linux problems
1-2 years programming (shell scripts, awk, Perl, C++ type programming
language)
BSCS/ BSEE or above
medium size company in bay area |
|
d****y
发帖数: 76 | 22 【 以下文字转载自 JobMarket 讨论区 】
发信人: dooffy (dooffy), 信区: JobMarket
标 题: Opening of Circuit Design Engineer position at a Silicon Valley company
发信站: BBS 未名空间站 (Thu Nov 10 15:49:32 2011, 美东)
A reputable IC design company is now hiring Circuit Design Engineer with the
focus on transistor level circuit design. Please find the detailed job
description at the end of this message. If you are well qualified, we would
like you to join us as soon as you can. For those who are still in the
middle of degree pr... 阅读全帖 |
|
c*******e
发帖数: 65 | 23 帮国内朋友发帖。谢谢~
Senior RF IC Designer ---- Nufront
Experienced RFIC designer contributed as a project leader of the RFIC
development group in Nufront, Beijing or Shanghai, China. The Chip design
focus is wireless radio transceiver for cellular systems. Experience in CMOS
RF& analog IC design is required. Knowledge of CMOS RF and analog IC debug
& characterization, device modeling, and design challenges in scaled CMOS
technologies as well as a strong academic and industry background is
strongly prefe... 阅读全帖 |
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h*******y
发帖数: 896 | 24 【 以下文字转载自 JobHunting 讨论区 】
发信人: heartaway (9527), 信区: JobHunting
标 题: 我们公司有芯片设计的位置 power management IC: analog, digital, layout
发信站: BBS 未名空间站 (Tue Jan 17 09:33:16 2012, 美东)
地点在Austin，方向是做power management IC， 工作位置是analog， digital
和layout工程师。老板说现在只招有工作经验的，如果有兴趣可以发简历给我，我的
email
地址是：b****[email protected] |
|
d**g
发帖数: 1031 | 25 Both.
Application engineer support, customer design such as EVM board layout,
customized schematic and layout design, business development,market
development, etc. |
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a*m
发帖数: 6253 | 26 【 以下文字转载自 JobHunting 讨论区 】
发信人: aTm (Aggie), 信区: JobHunting
标 题: Power Management IC design openings
发信站: BBS 未名空间站 (Sun Jul 1 20:32:57 2012, 美东)
If you are interested, please contact me here or "atm.mitbbs AT
gmail.com".
We are looking for fresh or experienced circuit designers, with very
attractive package. The location will be San Diego, CA, one of the best
places to live in the states.
The successful candidate will be involved in definition, design,
simulation, layout supervision, characte... 阅读全帖 |
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l**********7
发帖数: 614 | 27 谢谢回贴。
有道理，地线switch哪里来的过流保护，他们拿到人家芯片公司资料乱理解。
外部地就是external GND, 就是外部输入电源地。
我是想直接连，但他们说之前做esd的时候发现地线上的SWITCH被烧了。
但我做测试直接VSSE,VSSA相连加0电阻，发现不但没被烧而且ESD还过了。
其次，他们做layout的时候，几个芯片就split了几块地，然后每块地都用了个电容相
连。
感觉这个layout很怪，我是觉得肯定有问题。通常不是就单个地或者split模拟和数字
或系统吗？但不至于每个芯片都有个独立的GND PLANE吧，而且这3个芯片是相同的，那
如果5个，10个，都全分开不太搞笑了？
ground
protection |
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c*****e
发帖数: 43 | 28 遇到一个仿真的问题，大致情况是这样的：在layout画了一个two-port network，里面
用ADS Momentum得到的s paramater 然后转化成z parameter.这个转化用matlab 的
function或ADS自带的stoz()都算过，结果是一致的。 然后我把这个layout转化成一个
component, 用于我的一个简单的电路图中。这个电路图里面，我测量两个port的电压
V1, V2，和电流I1, I2，然后为了验证，我带入Z-parameter运算，照理来说应该要V=Z
*I, 可是等式左右不相等，并不是符号不对，而是数值相差太多。
不知道问题出在哪里？
另外我询问了agilent support,他们给了我一段摘抄于他们knowledge center的话，如
下。可我还是不懂，这里说的意思是有两组不同的z-parameter吗？我只听说过open
circuit下算出来的z-parameters.不知道我哪里理解错了.麻烦看看，感谢大家了。
Why (Z11)s are different?
Issue
I have a two port n... 阅读全帖 |
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a*m
发帖数: 6253 | 29 The successful candidate will be involved in research, definition, design,
simulation, layout supervision, characterization and release to production
of high-performance state of the art BiCMOS integrated circuits in the
following areas:
Power Management – LDOs, SMPS, Battery chargers, LED drivers, Charge Pumps,
Audio Amplifiers – Class D, AB, …
Interface Circuits –SPI, I2C, USB, …
Including the following functional blocks
Gain amplifiers
Bandgaps and references
Temperature sensors
Voltage monit... 阅读全帖 |
|
m********o
发帖数: 796 | 30 楼主背景：
PKU EE MS + BS(embedded system)
USA MS，目前phd,已quit，老板愿意签CPT
主要的project experience：
1：System Design for ARM9 Processor
(1) Minimum system design including on-board RAM and Flash interface, audio
peripheral circuit design using I2S control; schematic and 8-layer PCB
layout; hardware system integration and debug
(2) Linux kernel transplantation; audio data compression algorithm
implementation for Voice over IP (VoIP); application software development
with graphic user interface (GUI) using QT... 阅读全帖 |
|
s*****t
发帖数: 987 | 31 这个看下layout就立马明白了 同样的一个and gate layout可以有多种实现方法
finger越多footprint越大 驱动越强 |
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l********8
发帖数: 4 | 32 【 以下文字转载自 SanFrancisco 讨论区 】
发信人: lighten628 (realm), 信区: SanFrancisco
标 题: [提供内推] EDA product/application engineer
发信站: BBS 未名空间站 (Sun Feb 1 13:27:51 2015, 美东)
We are one of the top-four EDA companies, looking for an energetic product
application engineer to grow our business and global customers. Fresh
graduates are welcome to apply, and experienced candidates are highly
desired. Send me your resume or message me to know more about it. I can
provide a strong recommendation for the right pers... 阅读全帖 |
|
c*******y
发帖数: 60 | 33 今年底毕业，将发2个paper。 目前研究偏生物，与biofiltration有关。简历已经投了
n多了，只有两个回应，其中一个还是个process engineer， 跟环境不沾边（电面没什
么问题，但他们最后还是要了一个跟他们目前一个客户以前合作过的人）。大公司职位
看到很多，很多也是entry level的，我也是基本每周都投，大小公司都有，但都是石
沉大海。
个人觉得，经验少于一年，硕士，无人推荐，找工作完全就是碰运气。老板多年不跟工
业界联系了，帮不了什么忙。有个同学，硕士，不是环境的，找的是系里其他老师的推
荐，马上就拿到了good year的offer。
本人还是想进工业界，因为不太愿意走学术。贴下本人主要经历，请教环境方面的前辈
：我的简历还有哪些需要改进的地方？ 目前求职方向有哪些需要注意的？
硕士gpa3.9，国内本科给水排水工程，gpa3.5左右。
Environmental Engineer
An entry-level Environmental Engineer with excellent understanding in water/
wastewa... 阅读全帖 |
|
c*******y
发帖数: 60 | 34 今年底毕业，将发2个paper。 目前研究偏生物，与biofiltration有关。简历已经投了
n多了，只有两个回应，其中一个还是个process engineer， 跟环境不沾边（电面没什
么问题，但他们最后还是要了一个跟他们目前一个客户以前合作过的人）。大公司职位
看到很多，很多也是entry level的，我也是基本每周都投，大小公司都有，但都是石
沉大海。
个人觉得，经验少于一年，硕士，无人推荐，找工作完全就是碰运气。老板多年不跟工
业界联系了，帮不了什么忙。有个同学，硕士，不是环境的，找的是系里其他老师的推
荐，马上就拿到了good year的offer。
本人还是想进工业界，因为不太愿意走学术。贴下本人主要经历，请教环境方面的前辈
：我的简历还有哪些需要改进的地方？ 目前求职方向有哪些需要注意的？
硕士gpa3.9，国内本科给水排水工程，gpa3.5左右。
Environmental Engineer
An entry-level Environmental Engineer with excellent understanding in water/
wastewa... 阅读全帖 |
|
m*****e
发帖数: 44 | 35 我主要的疑问是怎么在3D Model中去清晰表示零件间的关系。比如第一个零件移动到A1
处，第二个零件就移动到B1处；一旦第一个零件移动到A2处，第二个零件就移动到B2。
从A1到A2的距离，应该可以推断B1到B2的距离，在AutoCAD里，平面的Layout中，这样
的关系很容易表示，零件间的尺寸也很容易从图上得到，而在3D的Model里，这样的关
系如何表示呢？窍门是什么呢？
我其实对具体的操作很熟悉，随机的帮助看了好多，但是就觉得我用的方法不对，总离
不开平面的Layout。或者说我没有学会用Solidworks的方法思考。 |
|
m*********y
发帖数: 127 | 36 纯借id发文……
我以前选的是d，主要是从能否成功build的角度看的……
c
recompiling
各库都已经编译过，即使增加新的constructor，导致如重载的变化、默认构造函数无
效，但是应该都会保留原有的行为，不会导致链接失败。
同意前面的，这个导致memory layout变化，确实会影响行为，带来很多不安全的因素
。但是应该也不会导致链接失败。
同意前面的，如果以前没有虚函数，现在会增加vtable，同样改变了memory layout…
…但是其他情况下，应该行为都没有变化，并且链接不会失败。
C++/C里面函数默认值应该是静态绑定的，增加默认参数仍然改变了函数的signature，
如果库里有调用的话，应该会导致链接失败 |
|
y****e
发帖数: 28 | 37 So the answer of the original question is to first define a null pointer of
the class and then read the memory layout in the debugger.
I don't like the second part. Is it ever possible to get the memory layout
without using the debugger?
A very strange interview question. |
|
D******n
发帖数: 2836 | 38 you mean u just go with the format SAS automatically assigns? thats not
very
good. In industry, the raw data should always come with a layout, u just
use that layout to read in your raw data. If not so, you have to look into
each field to figure it out. SAS gets it mostly right .
I guess u might be wrong about your statement in your first post too.
usually one row per record as well as for the header too. It might look
like
multiple rows in your text editor but it is technically just one row. |
|
z**k
发帖数: 378 | 39 layout或library(grid)
版上问问题的人为啥总是惜字如金
layout(matrix(c(1,1,1,2,2,2,3,3,4,4,5,5),2,6,byrow=T))
for (i in 1:5)
plot(rnorm(100)) |
|
c*****1
发帖数: 131 | 40 This problem occurs because you cannot export a table that contains more
than 65,000 rows by using the Export data with formatting and layout option.
To work around this problem, do not click Export data with formatting and
layout when you export a table that contains more than 65,000 rows.
Let me know if this works! |
|
t****a
发帖数: 1212 | 41 You cannot put all histogram into one figure.
If you try to put them into one jpg file or one pdf page, use jpeg() or pdf(
), and then layout(matrix(1:100,10,10)) before the loop and use dev.off()
after the loop. Take a look at layout(), jpeg(), pdf() function before start
doing this.
If you want to put all figures in 100 separated pages, simply use pdf()
before loop and dev.off() after loop.
You may want to try more advanced techniques such as histogram() in lattice
package. It would simply gen... 阅读全帖 |
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l******8
发帖数: 9475 | 42 其实大家早就料到可能会这样了.
十几年前就开始从网上抓特定网站的信息, 今年初还和朋友一起抓房地产信息. 如果
真想, 一个小时内可以扫描它多少遍. 只需要修改设置参数, 程序都不用改.
页面比较结构化, 比较好抓.
首页: 以下面结构为基准, 进行分解, 把文件名存好. 往下找, 翻页.
● pets版争论指南....
然后去调解析文件内容的程序.
以"
cellpadding="0">
我家两台Server, 一台运行程序永远抓首页的帖子和其内容, 另一台运行程序永远抓从
第二把页开始的帖子和其内容, |
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m****s
发帖数: 18160 | 43 ☆─────────────────────────────────────☆
laosong8 (吃喝玩乐坐汽车) 于 (Mon Nov 14 15:35:07 2011, 美东) 提到:
以下只是我的片面之词！
同时请求解封所有被PALA (天妒英才～～～)封的ＩＤ。
十指有长短， 哪能一般齐。 人非生而知之者，孰能无惑？ 闻道有先后，术业有专攻，如是而已。
人的经历不同， 对事物的看法可能就不会一样。 在互相解惑的过程中必定会产生争议， 在这个过程中“裁判（版主）就要保持中立。不可又当运动员， 同时又当裁判员。
为什么要弹劾他？
心胸狭窄， 不能保持中立; 官报私仇， 滥用职权， 有顺我者昌， 逆我者亡之心和
行动; 说话不文明， 时常带出威胁语气的字句; 有时没有分清是非的能力;
Paladino是PALA的马甲
1。 心胸狭窄， 不能保持中立。
证据：
http://www.mitbbs.com/article_t/pets/32285553.html
－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－
laosong8 (吃喝玩乐坐汽车... 阅读全帖 |
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L***n
发帖数: 25 | 44 Location: Medical device company in NYC
The Mixed Signal Electrical Design Engineer designs analog and digital
circuitry for new medical imaging products as well as improves circuitry in
existing products. Tasks include analyzing, designing, prototyping, and
testing analog, digital and support circuitry used in medical imaging
products. Responsibilities include documenting designs, working with other
engineering disciplines, and transitioning prototype designs to
manufacturing. Major responsibi... 阅读全帖 |
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M******a
发帖数: 6723 | 47 来自主题: Mod_CHN_Hist版 - 奉天兵工厂 https://wwiiafterwwii.wordpress.com/2017/04/03/mukden-arsenal-after-wwii/
Mukden Arsenal after WWII
April 3, 2017 jwh19752 Comments
(Zhang's Gate, the old entrance to Mukden Arsenal)
For people interested in Japanese firearms of WWII, the name Mukden Arsenal
is familiar. The history of the facility after Japan's defeat is less well
known. Under various names, it did survive for some time, producing an odd
mix of WWII weapons after the war's end.
(Mukden Arsenal proofmark during WWII)
Mukden an... 阅读全帖 |
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l******n
发帖数: 321 | 48 好郁闷!!!
今天在myspcae上闲逛,然后就逛到了花生地和猴子园,还有橙子林去了!
其实都不是本人,都是fans帮忙搞的!
当然我早就发现了张杰的,我也加为好友了!!
可是猴子园的layout就是用自己的图片!!
橙子林里也是一样的~
至于那个花生地就是一片蓝色的!
而我们张杰的呢.则是一片白底!!
请问哪个很懂这个的星星做一个张杰的layout好不好啊??我就可以用了啊!!!!
谢谢谢谢!! |
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w*******y
发帖数: 60932 | 49 Ive decided to compile some resources and tips that will allow you to get a
domain name, web hosting, a basic CMS, web apps and branded email for about
$10/yr.
I think that with a little work and compromise, this combination will be
more than suitable for 70% of people. If you require a shopping cart, FTP
access or any detailed custom development, move on this is not for you. This
is for small business owners who traditionally operate in the brick &
mortar realm who just want a web presence, gro... 阅读全帖 |
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w*******y
发帖数: 60932 | 50 Must register for Panasonic Purchase Program!
1. Go to epp.panasonic.com (no www)
2. Click on Sign Up
3. Use group ID NXT777
4. Log in and get sweet discounts! Woot!
Inside the site, look under Audio>Home Theater Systems>SC-BT230
Price is $230 + tax with free shipping!
This system has a Blu-Ray player while the Wal-Mart and ShopOnkyo home
theater deals only have a DVD player. Great match for your new BF TV deal!
Solid 4-star ratings on Amazon:
Link:
http://www.amazon.com/Panasonic-SC-BT23... 阅读全帖 |
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