I***a
发帖数: 704 | 1 Spice netlist和 Pspice netlist, Spectre netlist有哪些区别？ |
|
g*z
发帖数: 124 | 2 spice netlist is like English
pspice netlist is like American English
Spectre is like Spanish |
|
c*b
发帖数: 3126 | 3 extract netlist from SOC Encounter after placement&routing
or use "v2lvs" in Calibre
netlist)?
Thanks |
|
I***a
发帖数: 704 | 4 你要hspice netlist干什么？
如果是为了做LVS，直接把verilog netlist导入Cadence得到schematic，然后用Calibre/Assura做LVS |
|
L********3
发帖数: 2272 | 5 【 以下文字转载自 Stockcafeteria 俱乐部 】
发信人: Lincoln123 (Lincoln123), 信区: Stockcafeteria
标 题: Netlist 看来市场前景越来越好，是不是一只黑马
发信站: BBS 未名空间站 (Wed Jul 7 18:25:57 2010, 美东)
Netlist shares jump 19% on Dell announcement
Netlist (NLST) shares are up sharply after the company announced that Dell
has “qualified” its 512 MB and 1 GB flash-based cache subsystems to
support the company’s RAID storage applications.
This isn’t a contract, but it could give a boost to sales of the company’s
products to Dell storage cust... 阅读全帖 |
|
L********3
发帖数: 2272 | 6 Netlist shares jump 19% on Dell announcement
Netlist (NLST) shares are up sharply after the company announced that Dell
has “qualified” its 512 MB and 1 GB flash-based cache subsystems to
support the company’s RAID storage applications.
This isn’t a contract, but it could give a boost to sales of the company’s
products to Dell storage customers.
NLST today is up 47 cents, or 20.4%, to $2.77. |
|
r****e
发帖数: 122 | 7 我装了个cadence, analog design environment提取netlist时 对voltage source
不能提出type (pulse, sine etc).
对nmos pmos 也提不出model name...估计还有别的错误 是什么地方需要设定？Thanks! |
|
a******e
发帖数: 80 | 8 代人发帖，请指教，谢谢
我有一个数字设计，是在Cadence Virtuoso里用foundry提供的standard digital
cells建的 schematic，然后用"Virtuoso verilog environment for NC-Verilog"生成
verilog网表。在这个网表里，这些digital cell的连接是按端口的位置对应连接, 而
不是用端口名对应连接,比如:
NO2X1 I70 ( nQ, SET, Q);
NO2X1 I71 ( Q, nQ, RESET);
注： NO2X1是一个两输入NOR门
将这个网表作为输入文件导入到Encounter时，出现如下错误信息：
**ERROR: (SOCVL-349): Missing module definition in netlist for NO2X1.
**ERROR: (SOCVL-209): [./SR_latch_5V.v:16]: Parser does not handle
connection-by-position for this module.
at ,.
**ER |
|
I***a
发帖数: 704 | 9 top-level里有2个instance,
一个给的是spectre netlist,
另一个有schematic,这种情况如何仿真？ |
|
A***J
发帖数: 478 | 10 我做THESIS的时候的方法是，你先要用STANDARD CELL把那些NETLIST的东西CONVERT 成
SCHEMATIC,然后在用SPECTRE 仿真， CADENCE里面有个IMPORRT VERILOG的选项，但是
必须在导入前有STRARD CELL. |
|
L********3
发帖数: 2272 | 11 1.公司主营
designs, manufactures and sells memory subsystems primarily for the server, high-performance computing and communications markets. The Company's memory subsystems consist of dynamic random access memory integrated circuits (DRAM ICs), NAND flash memory (NAND) and other components assembled on a printed circuit board (PCB). The Company also designs custom semiconductor logic devices, which are integrated into its memory subsystems. Netlist was founded in 2000 and is headquartered in Irvine... 阅读全帖 |
|
f**********g
发帖数: 2252 | 12 Netlist HyperCloud(TM) Memory Achieves Compatibility Certification on Intel
Server Platforms from Computer Memory Test Labs
19 hours 49 minutes ago - PRN via Comtex
PR NewswireNetlist, Inc. (Nasdaq: NLST), a designer and manufacturer of high
-performance memory subsystems, today announced that its HyperCloud(TM)
memory module has achieved independent industry functional certification
from Computer Memory Test Labs (CMTL), a leading independent test lab for
memory modules and motherboard compatib... 阅读全帖 |
|
f**********g
发帖数: 2252 | 13 Netlist HyperCloud(TM) Memory Achieves Compatibility Certification on Intel
Server Platforms from Computer Memory Test Labs
19 hours 49 minutes ago - PRN via Comtex
PR NewswireNetlist, Inc. (Nasdaq: NLST), a designer and manufacturer of high
-performance memory subsystems, today announced that its HyperCloud(TM)
memory module has achieved independent industry functional certification
from Computer Memory Test Labs (CMTL), a leading independent test lab for
memory modules and motherboard compatib... 阅读全帖 |
|
l******h
发帖数: 2 | 14 Highly reputational company with very competitive compensation for all
positions.
Please send in your resume and position/positions you like to apply to my
email address below.
h*******[email protected]
All resumes will be deliver to hiring manager directly. Act fast!
Thanks!
Silicon Engineering Group
Sr. Physical Design Timing Engineer
Timing (STA) Manager
Senior Physical Design Engineer
CAD Manager - Front-End Design and Verification
Sr. CAD Engineer - Place & Route / Physical Design Engineer
Sr. CA... 阅读全帖 |
|
l******h
发帖数: 2 | 15 Highly reputational company with very competitive compensation for all
positions.
Please send in your resume and position/positions you like to apply to my
email address below.
h*******[email protected]
All resumes will be deliver to hiring manager directly. Act fast!
Thanks!
Silicon Engineering Group
Sr. Physical Design Timing Engineer
Timing (STA) Manager
Senior Physical Design Engineer
CAD Manager - Front-End Design and Verification
Sr. CAD Engineer - Place & Route / Physical Design Engineer
Sr. CA... 阅读全帖 |
|
a******e
发帖数: 331 | 16 Cadence can import .cdl to schematic and CDL is quite similar to Spice
netlist. If you are generating netlist by perl I think it should be easy for
you.
You also can try Laker, the netlist import to schematic is very good. It can
organize your netlist much better, such as put digital circuit as what we
normally see as buffer/NAND etc. and analog circuit as differential pairs,
current mirrors etc. |
|
d*****x
发帖数: 1520 | 17 【 以下文字转载自 Stock 讨论区 】
发信人: djbwsnx (跳大绳), 信区: Stock
标 题: 关于NLST被告的看法
发信站: BBS 未名空间站 (Tue Dec 1 00:09:52 2009, 美东)
今天，Netlist 被世仇inphi给狗咬狗，告了。其实Netlist公
司今年9月先对Inphi提起联邦诉讼，指控Inphi的iMB系列的隔离内存缓冲区集成电路侵
犯了Netlist公司的专利，没想到现在Inphi今天反过来告它了。我个人看好NLST因为
Netlist是第一家在原始设备制造商基础上为各大企业生产内存模块公司它推出虚拟化
，高密度的DDR3内存模块，这种模块将帮助服务器获取超出预期的主存容量。这与标准
服务器配置相比，能为X64服务器提供更多内存容量的能力当然是思科系统公司加利福
尼亚统一计算系统所属的B250-M1型刀片服务器和旗下的 C250-M1型机架式服务器的主
要卖点之一。这两款服务器都配置了特殊的内存专用集成电路，可以帮助思科公司的双
路至强5500服务器的主存容量最高达到384GB，一款12个内存插槽的标准服务器内存容
量最 |
|
r*******r
发帖数: 1014 | 18 SPECTRE:
SPecial Executive for Counter-intelligence, Terrorism, Revenge and Extortion |
|
T******T
发帖数: 3066 | 19 guess you played mass effect 2 ???
Extortion |
|
I***a
发帖数: 704 | 20 1， Design Compiler综合FPGA，提供的cell只包括LUT/register, 不包括swich box,
对吗？LUT的cell description一般是怎样的？
如何表示这个4-input LUT:
0000->可配置
0001->可配置
0010->可配置
...
1111-> 可配置
2. Design Compiler综合FPGA得到的是由LUT/register表示的netlist, 就必然包括了
对LUT的配置位，这些在netlist里面是如何体现的？
例如这个4-input LUT:
0000->1
0001->0
0010->0
...
1111-> 1
3. Design Compiler综合FPGA得到的是由LUT/register表示的netlist, 只包括对LUT的
配置位, 不包括LUT/register的Placement和Switch Box的配置位,
那么LUT/register的Placement和Switch Box的配置位是由什么工具得到的？
Thanks. |
|
I***a
发帖数: 704 | 21 extract 以后netlist里面加入了很多R,C,L
而且Transistor的instance name都变了，因为extract以后都flatten了。
如果想观察和extract前的netlist里一个对应的信号，
如何在extract 以后的netlist里定位到这个信号呢？
thanks. |
|
s*****t
发帖数: 987 | 22
RTL code
synthesis 工具 Synoposys ICC 或者Cadence RTL Compiler
过程就是调用fab的某个原件库，比如说TSMC 28nm lib 库里面包含了各种AND OR FF等等
综合工具自动用TSMC 28nm lib里面的已经layout好的各种库原件来表达你的RTL功能。
当然逻辑和你的Verilog code 是等价的 有自动工具去比较RTLcode 和综合过后的
verilog netlist
这个综合过后的verilog netlist已经包含了物理信息了，和你的FPGA综合是一样的，
只不过FPGA用的是内部的各种资源
Layout 工具如ICC，读入综合后的verilog netlist, 然后会调用TSMC 28nm lib里面对
应的layout好的各种AND OR FF等等 这个时候就能看到你的版图了 |
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f*******r
发帖数: 55 | 23 【 以下文字转载自 JobMarket 讨论区 】
发信人: frankfeir (frankfeir), 信区: JobMarket
标 题: Synopsys R&D positions in MA
发信站: BBS 未名空间站 (Wed Feb 25 14:07:46 2015, 美东)
There are 2 openings in Synopsys VG team in marlborough, ma. If you are
interested, please send resumes to [email protected]
/* */
R&D Engineer, Staff
The Engineer will be part of the Software R&D team based in Marlborough, MA.
In this role you will contribute to the development of simulation, emulation
and FPGA prototyping software, includi... 阅读全帖 |
|
f*******r
发帖数: 55 | 24 There are 2 openings in Synopsys VG team in marlborough, ma. If you are
interested, please send resumes to [email protected]
/* */
R&D Engineer, Staff
The Engineer will be part of the Software R&D team based in Marlborough, MA.
In this role you will contribute to the development of simulation, emulation
and FPGA prototyping software, including the support and modeling of the
prototyping board, automatic partitioning, placement and routing on the
board, timing analysis and timing optimiza... 阅读全帖 |
|
f*******r
发帖数: 55 | 25 【 以下文字转载自 JobMarket 讨论区 】
发信人: frankfeir (frankfeir), 信区: JobMarket
标 题: Synopsys R&D positions in MA
发信站: BBS 未名空间站 (Wed Feb 25 14:07:46 2015, 美东)
There are 2 openings in Synopsys VG team in marlborough, ma. If you are
interested, please send resumes to [email protected]
/* */
R&D Engineer, Staff
The Engineer will be part of the Software R&D team based in Marlborough, MA.
In this role you will contribute to the development of simulation, emulation
and FPGA prototyping software, includi... 阅读全帖 |
|
L********r
发帖数: 59 | 26 Job Category Design Engineering
Country USA
Location San Jose (CA)
Job Description
The role will involve: physical implementation for integration of analog
components and digital circuits on DDR PHY. Working closely with digital
design engineer, verification engineers, analog engineers, mixed signal
engineers.
Job Purpose
The role will involve: physical imple... 阅读全帖 |
|
c*********6
发帖数: 858 | 27 You can export the netlist from the schematics in the Cadence Capture. The
netlist is just a file that shows how the components interconnect. |
|
f********o
发帖数: 2181 | 28 用某个公司提供的digital standard library
他们把电路图和版图都给加密了
现在想在cadence virtuoso里面仿真那些数字模块(INV, XOR, NAND, etc)
没有电路图, 只有cmos_sch格式的"Cellview for black box netlisting"
我试了Spectreverilog, 说这个不是digital block, 不能仿真
直接用Spctre生成的netlist, 那些数字模块都是空的
有没有什么办法仿真?
多谢 |
|
a******e
发帖数: 331 | 29 I am not a SOC encounter expert and using Synopsys.
I think SOC Encounter same as other Place & Routing tools, based on
constraints to determine the buffer stages and driving strength. In Design
Compiler, you can set dont touch on the netlist and buffers to keep the
netlists. You can find equivalent command in SOC encounter.
very
the |
|
a******e
发帖数: 331 | 30 To get power, after Gate level simulation, get .VCD file, read into
primepower and report peak and average power. But you can also get average
power if you have switching activity information for the design and the
software will propagate for you.
If you are using <130nm process, DC netlist/SDF is not good enough and
should use P&R netlist and SDF because of the interconnect effects. To write
out SDF from DC, I suggest you use GUI mode in design_vision if you are not
so familiar with TCL.
do |
|
g*g
发帖数: 6908 | 31 sdf是和netlist一起，你用这俩来运行仿真，得到比较准确的vcd或者saif
没有sdf，只用netlist,你的gate-level simulation都未必能通过吧，你用zero dealy
还是unit delay？就算通过了toggle information也不准确
is
What |
|
a*m
发帖数: 6253 | 32 Symbol is to identify the pins for the port connectivity.
In your netlist, you need to define the pins for the symbol.
BTW, it is way easier to generate the schematic instead of import your
netlist. Why bother? |
|
H****E
发帖数: 444 | 33 有一部分比较多但是比较有规律的电路打算用perl来写成netlist，然后把这部分作为
一个symbol
放到图形界面下连一个比较简单的电路，请教一下，我自己写的netlist文件加了pin之
后应该存
成什么样的格式呢？是否通过icfb的File-->Import来导入？
谢啦！ |
|
a******e
发帖数: 331 | 34 你有Synopsys的Solvnet户头吗？有的话可以去以下下载
http://www.synopsys.com/Community/UniversityProgram/Pages/defau
90nm Generic Library Content
Technology Kit
The Technology Kit includes a databook and user guide, symbols, .lib,
Verilog and VHDL simulation models, DRC and LVS decks, HSPICE netlists,
extracted C/RC netlists, GDSII layout views, LEF files, generic SPICE models
, fram views, layout views and runset files.
Digital Standard Cell Library
The Digital Standard Cell Library consists of 340 cells to optimi... 阅读全帖 |
|
w*****n
发帖数: 27 | 35 在用calibre run lvs时，要求在inputs的layout tab中载入layout netlist file，我
不知道这个是从哪产生的？我现在已经有了gds的文件了，这个与layout netlist文件
是什么关系呢？ |
|
w*****r
发帖数: 348 | 36 Anybody has the experience? Detail procedure is greatly appreciated! Thanks
a lot in advance. |
|
|
b********k
发帖数: 427 | 38 多谢！
.OP xxxns 这个命令比较好用，但是得到的OP的值好像并不能加载到HSPICE仿真中。
.inc 好像只能是include netlist吧，op命令保存的dp文件不是netlist的格式的。如果
你用inc命令来装载dp文件成功过，还请你明示，谢谢。
.ic 用来设置初始值，但是对于BJT只有vbe，bce两个参数。用这两个参数来完全设置
BJT的状态是不够的，也就是说对于给定的vbe和bce，BJT电路结构内部的其他原件的状
态是不确定的。
OP命令得到的是dp文件，我得到的关于BJT的dp文件格式如下：
subckt
element 0:q1
model 0:BJT
ib 5.8821736535p
ic 52.4261389381p
vbe 392.2462191601m
vce 6.6666661775
vbc -6.2744199583
vs ... 阅读全帖 |
|
f*******r
发帖数: 55 | 39 【 以下文字转载自 JobMarket 讨论区 】
发信人: frankfeir (frankfeir), 信区: JobMarket
标 题: Synopsys R&D positions in MA
发信站: BBS 未名空间站 (Wed Feb 25 14:07:46 2015, 美东)
There are 2 openings in Synopsys VG team in marlborough, ma. If you are
interested, please send resumes to [email protected]
/* */
R&D Engineer, Staff
The Engineer will be part of the Software R&D team based in Marlborough, MA.
In this role you will contribute to the development of simulation, emulation
and FPGA prototyping software, includi... 阅读全帖 |
|
|
|
d*******l
发帖数: 110 | 42 【 以下文字转载自 EE 讨论区 】
发信人: dumpitall (dumpitall), 信区: EE
标 题: 替朋友贴个硬件位置
发信站: BBS 未名空间站 (Fri Apr 30 22:28:41 2010, 美东)
站内发简历，我会转给那个经理。
》》》》》》》》》》》》》》》
Located at the heart of Telecom Corridor in Richardson, Texas, a fast
growing wireless communication startup is looking for a hardware test intern.
· RESPONSIBILITIES:
· Assemble and test prototype electronic and rf assemblies
· Design wiring harnesses and system cabling
· Check schematic netlists and BOMs
· Coordinate fabrication and turn-k |
|
S***l
发帖数: 383 | 43 Job Description: Sr. ASIC DFT Engineer
As part of the Central DFT group, you will be responsible for architect,
implementation, verification, and lab bring-up of the DFT and DFM solutions
for the advanced and comprehensive Design for Test/Manufacturing (DFT/DFM)
features for the system on a chip integrated in the industry leading edge
network products.
Core Responsibilities:
• ASIC DFT lead to top level architect, implement and verification of
DFT features including MBIST, Logic BIST,... 阅读全帖 |
|
O******2
发帖数: 210 | 44 数字IC工程师的技能树 （zz）
http://bbs.eetop.cn/viewthread.php?tid=320244
今天与同事聊起了IC工程师的修养等问题，结合不久前的一个想法，总结成文，抛砖引
玉，欢迎讨论和补充，转载请注明。
RTL语言仅仅就是Diablo里面女巫的火球。。。是首个技能，但你升到20级也就是个火
球。。。当然对别的技能是有加成的哦
其他主要技能是，
算法逻辑设计与IP集成评估:
设计的要求基本要看得懂算法文档做实现，定点化和一些数学基础。特定模块的集成要
求一般有相应知识背景，遇到问题能够debug进去。
SoC逻辑设计与IP集成评估:
总线，DMA，或者一些挂在总线上的内部设备
接口模块逻辑设计与IP集成评估:
DDR,HDMI，Tunner,AFE,一些非数字信号或者Phy的接口,通常都会从I2C入手，不要光盯
着逻辑哦，也可以看看上拉电阻的阻值是怎么算的么,这块上板调试的时间会比coding
时间长的多。。。
Chip Level模块设计:
这个基本每颗芯片都是独特的，也是关键的，涉及到clock gen, pad 复用,power
domain控制... 阅读全帖 |
|
x**1
发帖数: 892 | 45 欢迎站内投条
http://ch.tbe.taleo.net/CH03/ats/careers/searchResults.jsp;jses
3492 Design Engineer, Senior MTS US-CA-San Jose
3743 Design Engineer US-CA-San Jose
3920 Design Verification Engineer, Senior US-CA-San Jose
3962 ASIC Engineer US-CA-San Jose
4004 Distinguished Product Planning Manager, Platform Products US-CA-
San Jose
4020 Physical Design Engineer US-CA-San Jose
4024 Netlisting Build Engineer US-CA-San Jose
4043 Design Verification Lead Architect... 阅读全帖 |
|
f********e
发帖数: 325 | 46 The successful candidate will join a highly talented, dynamic group of
engineers within Power Conversion Business Group to develop state of the art
AC/DC power control and solid state lighting control products. Individual
in this role is responsible for all aspect of digital physical design and
implementation from RTL to GDS design flow covering Place & Route and other
digital backend functions including synthesis, STA, DFT and LEC.
RESPONSIBILITIES:
. Lead the development of all aspects of the ... 阅读全帖 |
|
f*******r
发帖数: 55 | 47 另外两个组在招软件研发工程师，为了避免和之前的职位混淆，另外开了一个新贴。因
为做的是同一个产品，要求和之前差不多。有意者请发简历至[email protected]
/* */
具体的Job Description如下：
职位一：
Synopsys - Marlboro MA (Boston area) - Full time - C++ place & route tool -
New graduate / Master degree
The ZeBu [1] backend team, working on compiler for the ZeBu emulator, is
expanding fast. The routing team is looking for people excited by challenges
compile time by proposing new ideas, implementing them, constitutes the
bulk of the work.
We are looking for people with c... 阅读全帖 |
|
g****e
发帖数: 141 | 48 plz send resume to g****[email protected]
thanks
Job Description:
Design, develop and document RF board level hardware design from concept
through to production. Coordinate and participate in hardware product
development activities. Responsible for schematic capture, netlist
generation, BOM generation and circuit board layout. Perform lab testing (
DVT, HVT and SVT) and troubleshooting as needed. Take a collaborative design
and validation approach in working with multi-functional team of PCB,
hardwa... 阅读全帖 |
|
s*******d
发帖数: 82 | 49 Netlist, Inc. (NASDAQ: NLST) 8.9% LOWER; filed a registration with the U.S.
Securities and Exchange Commission today to sell, from time to time, up to $
30 million in Common Stock, Preferred Stock, Warrants, Depository Shares,
Units, or any combination thereof. |
|
a*****e
发帖数: 1717 | 50 By Joshua Fineman
Oct. 12 (Bloomberg) -- Netlist rose as much as 21%, most
in 3 months, on volume of 390% of 3-mo daily avg. after
receiving a patent for circuit with flexible portion. |
|
