n*********h
发帖数: 98 | 1 代友转发，请勿回信箱，直接发信至 [email protected]
/* */。谢谢！
=====================================================================
We are a fast-growing IC design company located in Silicon Valley,
currently we have one opening for SERDES system architect; please send
your resume to [email protected]
/* */ if interested.
Job description: SERDES System Architect
- Architecture definition and verification for high-speed long-reach
SerDes interfaces (up to 56Gbps)
- Serial link modeling and link ... 阅读全帖 |
|
n*********h
发帖数: 98 | 2 代友转发，请勿回信箱，直接发信至 [email protected]
/* */。谢谢！
=====================================================================
We are a fast-growing IC design company located in Silicon Valley,
currently we have one opening for SERDES system architect; please send
your resume to [email protected]
/* */ if interested.
Job description: SERDES System Architect
- Architecture definition and verification for high-speed long-reach
SerDes interfaces (up to 56Gbps)
- Serial link modeling and link ... 阅读全帖 |
|
l**k
发帖数: 160 | 3 A,B,L三家都有serdes，其中A做的最好。A合并L的时候把L的serdes裁了一大半。现在
合并B，看不出需要B家serdes的很大的必要性。
反而是B家的Ethernet会比较安全，因为A没有。
[在 zjy829 (大神勿喷) 的大作中提到：]
：扯。lsi家serdes那点东西能跟b家比？
：
：........... |
|
m****s
发帖数: 18160 | 4 【 以下文字转载自 EE 讨论区 】
发信人: mbta (mbta), 信区: EE
标 题: 湾区serdes I/O team招junior analog & mixed signal IC designer
发信站: BBS 未名空间站 (Wed Aug 28 16:56:26 2013, 美东)
湾区知名公司的serdes team招junior analog IC designer。待遇中上。做的东西是
cutting edge的，个人觉得比较有意思。绿卡政策友好。
请PM。最好有一段简单的介绍，gpa，学校，course focus，project经历，research。
。。这种。我的感觉，老板对人的要求比较高。
PS：如果有工作经历更好，老板会根据背景给title，不仅仅限于junior。 |
|
m****s
发帖数: 18160 | 5 【 以下文字转载自 EE 讨论区 】
发信人: mbta (mbta), 信区: EE
标 题: 湾区serdes I/O team招junior analog & mixed signal IC designer
发信站: BBS 未名空间站 (Wed Aug 28 16:56:26 2013, 美东)
湾区知名公司的serdes team招junior analog IC designer。待遇中上。做的东西是
cutting edge的，个人觉得比较有意思。绿卡政策友好。
请PM。最好有一段简单的介绍，gpa，学校，course focus，project经历，research。
。。这种。我的感觉，老板对人的要求比较高。
PS：如果有工作经历更好，老板会根据背景给title，不仅仅限于junior。 |
|
B********e
发帖数: 1199 | 6 【 以下文字转载自 EE 讨论区 】
发信人: BattleMage (法师), 信区: EE
标 题: two openings in SerDes Characterization in a big company
发信站: BBS 未名空间站 (Wed Oct 22 17:53:51 2014, 美东)
SerDes Characterization in a big company in San Diego (not Qcom)
Circuit or DSP preferred.
If fresh graduates, semiconductor, photonics, or other EE/EECS are fine, too.
PM me if you are interested. |
|
R***s
发帖数: 302 | 7 【 以下文字转载自 EE 讨论区 】
发信人: Rains (雨), 信区: EE
标 题: Job Opening: Broadcom, Irvine, SerDes
发信站: BBS 未名空间站 (Fri Oct 30 18:58:38 2015, 美东)
My group has several job openings for Analog/Mixed-Signal designers in a
SerDes group, located at Broadcom Irvine Campus. We're also looking for one
digital designer and an intern position. If you're interested, please
contact me through BBS email system first. I can give you more details,
including potential impact from pending AVAGO merger. Thanks. |
|
m****s
发帖数: 18160 | 8 【 以下文字转载自 Returnee 讨论区 】
发信人: ICdesign2011 (ICdesign), 信区: Returnee
标 题: 高薪诚聘高速模拟 SERDES 设计主管
发信站: BBS 未名空间站 (Thu Nov 22 04:18:37 2012, 美东)
We are an innovative ASIC technologies and networking company near by
Shanghai,China. We are looking for some Senior Design management on High
Speed mixed-signal circuity(over 10Ghz) Design & implementation. We will
offer very good compensation on the qualified candidate. If you are
interested in them, please contact with us.
Job description:
Design and sim... 阅读全帖 |
|
m****s
发帖数: 18160 | 9 【 以下文字转载自 EE 讨论区 】
发信人: mbta (mbta), 信区: EE
标 题: 湾区serdes I/O team招junior analog & mixed signal IC designer
发信站: BBS 未名空间站 (Wed Aug 28 16:56:26 2013, 美东)
湾区知名公司的serdes team招junior analog IC designer。待遇中上。做的东西是
cutting edge的，个人觉得比较有意思。绿卡政策友好。
请PM。最好有一段简单的介绍，gpa，学校，course focus，project经历，research。
。。这种。我的感觉，老板对人的要求比较高。
PS：如果有工作经历更好，老板会根据背景给title，不仅仅限于junior。 |
|
R***s
发帖数: 302 | 10 【 以下文字转载自 EE 讨论区 】
发信人: Rains (雨), 信区: EE
标 题: Job Opening: Broadcom, Irvine, SerDes
发信站: BBS 未名空间站 (Fri Oct 30 18:58:38 2015, 美东)
My group has several job openings for Analog/Mixed-Signal designers in a
SerDes group, located at Broadcom Irvine Campus. We're also looking for one
digital designer and an intern position. If you're interested, please
contact me through BBS email system first. I can give you more details,
including potential impact from pending AVAGO merger. Thanks. |
|
R***s
发帖数: 302 | 11 【 以下文字转载自 EE 讨论区 】
发信人: Rains (雨), 信区: EE
标 题: Job Opening: Broadcom, Irvine, SerDes
发信站: BBS 未名空间站 (Fri Oct 30 18:58:38 2015, 美东)
My group has several job openings for Analog/Mixed-Signal designers in a
SerDes group, located at Broadcom Irvine Campus. We're also looking for one
digital designer and an intern position. If you're interested, please
contact me through BBS email system first. I can give you more details,
including potential impact from pending AVAGO merger. Thanks. |
|
R***s
发帖数: 302 | 12 【 以下文字转载自 EE 讨论区 】
发信人: Rains (雨), 信区: EE
标 题: Job Opening: Broadcom, Irvine, SerDes
发信站: BBS 未名空间站 (Fri Oct 30 18:58:38 2015, 美东)
My group has several job openings for Analog/Mixed-Signal designers in a
SerDes group, located at Broadcom Irvine Campus. We're also looking for one
digital designer and an intern position. If you're interested, please
contact me through BBS email system first. I can give you more details,
including potential impact from pending AVAGO merger. Thanks. |
|
L********r
发帖数: 59 | 13 FPGA Engineer:
1. Familiar with Xilinx FPGA system
2. Familiar with Cadence Palladium
3. DSP and communication background is a plus
Analog IC design Engineer (SERDES)
1. Familiar with I/O design
2. Familiar with high-speed serdes
3. Experience on PCIe/SATA and DDR
Analog IC design Engineer (SRAM)
1. Responsible for design and verification of integrated IP blocks
2. Responsibilities could include analog and digital simulation, static
timing analysis, electrical rules verification, contention an... 阅读全帖 |
|
c*******s
发帖数: 735 | 14 挺好的。现在Serdes在Mobile领域中用途越来越多。Mobile device和其他终端的in
terface都是Serdes实现的。 |
|
n******h
发帖数: 2544 | 15 这个真心危险，B家的SerDes和Avago LSI都重叠，Ava go LSI工资结构低，Broadcom这
一块优势不突出，又贵。
所以直接SerDes相关的前景不看好。
one |
|
z****9
发帖数: 632 | 16 扯。lsi家serdes那点东西能跟b家比？
该去去，B家serdes不会有问题 |
|
f****y
发帖数: 33 | 17 本公司在国内从事高速集成电路开发设计,现在诚聘做高速 IO (SERDES)的海外优秀人
才. 待遇非常优厚.如有兴趣,或要了解更多详情, 可以站内联系我. |
|
f****y
发帖数: 33 | 18 本公司在国内从事高速集成电路开发设计,现在诚聘做高速 IO (SERDES)的海外优秀人
才. 待遇非常优厚.如有兴趣,或要了解更多详情, 可以站内联系我. |
|
I**********1
发帖数: 32 | 19 We are an innovative ASIC technologies and networking company near by
Shanghai,China. We are looking for some Senior Design management on High
Speed mixed-signal circuity(over 10Ghz) Design & implementation. We will
offer very good compensation on the qualified candidate. If you are
interested in them, please contact with us.
Job description:
Design and simulate mixed-signal circuitry for high-speed transceiver cores
or products;
Create design documents based on the mixed-signal design flow;
Sup... 阅读全帖 |
|
f****y
发帖数: 33 | 20 本公司在国内从事高速集成电路开发设计,现在诚聘做高速 IO (SERDES)的海外优秀人
才. 待遇非常优厚.如有兴趣,或要了解更多详情, 可以站内联系我. |
|
I**********1
发帖数: 32 | 21 We are an innovative ASIC technologies and networking company near by
Shanghai,China. We are looking for some Senior Design management on High
Speed mixed-signal circuity(over 10Ghz) Design & implementation. We will
offer very good compensation on the qualified candidate. If you are
interested in them, please contact with us.
Job description:
Design and simulate mixed-signal circuitry for high-speed transceiver cores
or products;
Create design documents based on the mixed-signal design flow;
Sup... 阅读全帖 |
|
m*z
发帖数: 644 | 22 EE博士，SerDes及混合信号方向，经验丰富，求审稿。 |
|
c******e
发帖数: 56 | 23 【 以下文字转载自 EE 讨论区 】
发信人: carlisle (hip,hip,horaay), 信区: EE
标 题: Broadcom奥斯汀job opening - SerDes Firmware Engineer - Senior Staff
发信站: BBS 未名空间站 (Sun Nov 2 09:27:54 2014, 美东)
http://jobs.broadcom.com/job/Austin-Senior-Level-Firmware-Engin
属核心产品线，roadmap完备。
已面试两，实在是。。。不怎么match。
Fresh grad如果有国内相关工作经验可以考虑。 |
|
f****y
发帖数: 33 | 24 本公司在国内从事高速集成电路开发设计,现在诚聘做高速 IO (SERDES)的海外优秀人
才. 待遇非常优厚.如有兴趣,或要了解更多详情, 可以站内联系我. |
|
n*********h
发帖数: 98 | 25 Hi guys, we are a fast-growing start-up in Silicon Valley developing cutting
-edge SerDes technology; currently we have multiple job openings in high-
speed analog/mixed-signal design (wireline transceiver, PLL) at all
experience levels. Please contact me at h***********[email protected] if
interested.
Thanks!
|
|
r*******r
发帖数: 308 | 26 indeed上湾区也没几个serdes design的职位啊。 |
|
s********9
发帖数: 14 | 27 搭车同问，作serdes电路前途如何？是不是以后工艺到头了速度也就上不去了？ |
|
d********i
发帖数: 91 | 28 工艺到头电路应该没办法了，带宽在那呢，或许要从调制方式上下功夫？感觉SerDes不
需要很多人做，不知道工作好不好找？ |
|
c*******s
发帖数: 735 | 29 今年H1b可能要用完了,身份是个大问题.湾区Serdes机会挺多的. |
|
w******4
发帖数: 488 | 30 RT. Fresh PhD in analog IC design， 去做高速serdes前途好吗？Career path会怎
样？ |
|
|
z****n
发帖数: 5870 | 32 先做 高速serdes 等过几年看看不好的话以后再慢慢转呗。要是在大公司就更容易转了
。 |
|
c*****c
发帖数: 5 | 33 做模拟的话，个人觉得不是个好的选择。SerDes基本以数字电路为主，花很多时间检查
timing.对于做模拟或者射频电路打基础很不利。如果一开始就选择这个方向，以后很
难换到别的领域。 |
|
B********e
发帖数: 1199 | 34 SerDes Characterization in a big company in San Diego (not Qcom)
Circuit or DSP preferred.
If fresh graduates, semiconductor, photonics, or other EE/EECS are fine, too.
PM me if you are interested. |
|
R***s
发帖数: 302 | 35 My group has several job openings for Analog/Mixed-Signal designers in a
SerDes group, located at Broadcom Irvine Campus. We're also looking for one
digital designer and an intern position. If you're interested, please
contact me through BBS email system first. I can give you more details,
including potential impact from pending AVAGO merger. Thanks. |
|
R***s
发帖数: 302 | 36 My group has several job openings for Analog/Mixed-Signal designers in a
SerDes group, located at Broadcom Irvine Campus. We're also looking for one
digital designer and an intern position. If you're interested, please
contact me through BBS email system first. I can give you more details,
including potential impact from pending AVAGO merger. Thanks. |
|
w******3
发帖数: 30 | 37 We have opening on Analog IC design position at various levels. If have high
speed Serdes design experience, it's plus.
The company is at Silicon Valley and it's a start up.
Anybody has interests, can connect with me. |
|
l******h
发帖数: 2 | 38 Highly reputational company with very competitive compensation for all
positions.
Please send in your resume and position/positions you like to apply to my
email address below.
h*******[email protected]
All resumes will be deliver to hiring manager directly. Act fast!
Thanks!
Silicon Engineering Group
Sr. Physical Design Timing Engineer
Timing (STA) Manager
Senior Physical Design Engineer
CAD Manager - Front-End Design and Verification
Sr. CAD Engineer - Place & Route / Physical Design Engineer
Sr. CA... 阅读全帖 |
|
l******h
发帖数: 2 | 39 Highly reputational company with very competitive compensation for all
positions.
Please send in your resume and position/positions you like to apply to my
email address below.
h*******[email protected]
All resumes will be deliver to hiring manager directly. Act fast!
Thanks!
Silicon Engineering Group
Sr. Physical Design Timing Engineer
Timing (STA) Manager
Senior Physical Design Engineer
CAD Manager - Front-End Design and Verification
Sr. CAD Engineer - Place & Route / Physical Design Engineer
Sr. CA... 阅读全帖 |
|
w*******e
发帖数: 285 | 40 我现在需要在hive里面用我自己的serde，然后我希望serde能用jni调用我线程的c++程
序，这样我就不需要用java重写。
我现在遇到的问题是首先运行add jar 可以把 serde本身的jar 文件加进去，但是再用
add file 把我的jni xxx.dll或者libxxx.so加上运行就总是找不到class。我在网上
search了半天也没有找到类似的，请问有什么例子可以参考吗？我似乎看到过peking2
有一篇blog讲过hadoop call jni的方法，但是现在找不到在哪里了？多谢帮忙。
add jar xxxSerDe.jar
add file xxx.dll
CREATE EXTERNAL TABLE ...
ROW FORMAT SERDE 'com.cloudera.hive.serde.XXXSerDe' |
|
L***o
发帖数: 77 | 41 请站内回复或发信到站内邮箱留下联系方式
You don't have to send me your resume now; I will give you my company email
address for resume purpose. You resume will forwarded to my manager directly
if there is a possible match.
美国公司，新加坡分公司
SERDES Mixed Signal Design Engineer
Description
Each designer is responsible for the functionality and quality of
their designs and insuring that they work correctly in the overall
system.
The candidate should have expertise in some (or preferably all) of the
following areas:
* ... 阅读全帖 |
|
L***o
发帖数: 77 | 42 请站内回复或发信到站内邮箱留下联系方式
You don't have to send me your resume now; I will give you my company email
address for resume purpose. You resume will forwarded to my manager directly
if there is a possible match.
美国公司，新加坡分公司
SERDES Mixed Signal Design Engineer
Description
Each designer is responsible for the functionality and quality of
their designs and insuring that they work correctly in the overall
system.
The candidate should have expertise in some (or preferably all) of the
following areas:
* ... 阅读全帖 |
|
L***o
发帖数: 77 | 43 请站内回复或发信到站内邮箱留下联系方式
You don't have to send me your resume now; I will give you my company email
address for resume purpose. You resume will forwarded to my manager directly
if there is a possible match.
美国公司，新加坡分公司
SERDES Mixed Signal Design Engineer
Description
Each designer is responsible for the functionality and quality of
their designs and insuring that they work correctly in the overall
system.
The candidate should have expertise in some (or preferably all) of the
following areas:
* ... 阅读全帖 |
|
L********r
发帖数: 59 | 44
FPGA engineer, analog design (Serdes) engineer, analog design (SRAM)
engineer and IC layout engineer
FPGA Engineer:
1. Familiar with Xilinx FPGA system
2. Familiar with Cadence Palladium
3. DSP and communication background is a plus
Analog IC design Engineer (SERDES)
1. Familiar with I/O design
2. Familiar with high-speed serdes
3. Experience on PCIe/SATA and DDR
Analog IC design Engineer (SRAM)
1. Responsible for design and verification of integrated IP blocks
2. Responsibilities could inclu... 阅读全帖 |
|
w7
发帖数: 76 | 45 正在找工作当中，一直做的的东西偏重于high-speed I/O方面，也就是high speed
serial serdes，（一般serdes包括I/O driver, PLL, CDR, Equalizer）等等。在学校
期间对于power management，RF IC都有涉猎，但不是完全花时间在上面，所以也就是
有些皮毛的知识，做过一些相关的project而已。通过找工作，越发感觉high-speed I/
O不是个主流的方向，一些recruiter甚至认为那就是digital ckt design（虽然我个人
不同意这点）。确实Serdes处理的是大信号的东西，但是实现的基础还是analog based
的，尤其在速度越来越高的时候。
我还是希望能转到做一些hardcore analog的block，power management 是一方面，RF/
base band 是另一方面。因为第一个job对carrer path非常重要，所以有些困惑。不知
道interface (high speed I/O) 这方面以后的发展会怎样。有industry的老革命能不
能给我们讲一 |
|
m*****t
发帖数: 3477 | 46 【 以下文字转载自 Working 讨论区 】
发信人: Lirio (lirio), 信区: Working
标 题: Mixed Signal Design Engineer Opening in SINGAPORE
发信站: BBS 未名空间站 (Fri Dec 24 00:30:53 2010, 美东)
请站内回复或发信到站内邮箱留下联系方式
You don't have to send me your resume now; I will give you my company email
address for resume purpose. You resume will forwarded to my manager directly
if there is a possible match.
美国公司，新加坡分公司
SERDES Mixed Signal Design Engineer
Description
Each designer is responsible for the functionality and quality of
their designs... 阅读全帖 |
|
n*********h
发帖数: 98 | 47 *********************************************
代友转发，请勿回信箱，直接发信给联系人邮件。谢谢！
*********************************************
We are a fast-growing company located in Silicon Valley,
and currently have a few job openings on high-speed SerDes design as
following; please feel free to send your resume to
[email protected]
/* */ if interested.
-> Job opening 1: Analog/Mixed-Signal IC Design Engineer
Ideal candidates should have previous circuit-design experiences in at
least one of the following: CDR,... 阅读全帖 |
|
L********r
发帖数: 59 | 48 FPGA Engineer:
1. Familiar with Xilinx FPGA system
2. Familiar with Cadence Palladium
3. DSP and communication background is a plus
Analog IC design Engineer (SERDES)
1. Familiar with I/O design
2. Familiar with high-speed serdes
3. Experience on PCIe/SATA and DDR
Analog IC design Engineer (SRAM)
1. Responsible for design and verification of integrated IP blocks
2. Responsibilities could include analog and digital simulation, static
timing analysis, electrical rules verification, contention an... 阅读全帖 |
|
m****l
发帖数: 17 | 49 I have two opening in my group:
One principal level with
1. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Another one sr. principal level with
1. CMOS Image pixel design experience
2. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Need Citizenship or PR
Send me email |
|
m****l
发帖数: 17 | 50 I have two opening in my group:
One principal level with
1. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Another one sr. principal level with
1. CMOS Image pixel design experience
2. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Need Citizenship or PR
Send me email |
|
