f****3
发帖数: 502 | | E*****a
发帖数: 757 | 2 这是mosfet push pull 输出级吧？
【在 f****3 的大作中提到】
: 见附件，多谢！
| f****3
发帖数: 502 | | I***a
发帖数: 704 | 4 pfet和nfet反了
【在 E*****a 的大作中提到】
: 这是mosfet push pull 输出级吧？
| E*****a
发帖数: 757 | 5 所以是push pull，如果反过来，是inverter
【在 I***a 的大作中提到】
: pfet和nfet反了
| E*****a
发帖数: 757 | 6 simulate一下吧。
上下都应该有个threshold saturation
【在 f****3 的大作中提到】
: 嗯，请问直流转换曲线应该是啥样的
| f****3
发帖数: 502 | 7 这是答案，我不明白为什么输入1.8至3.2，输出要钳制在2.5V，为什么不是输出一直
follow输入呐。
【在 f****3 的大作中提到】
: 见附件，多谢！
| E*****a
发帖数: 757 | 8 你要去翻一下push-pull stage的书。
两端各减掉0.7V你应该是懂的，因为上下都有threshold
中间的叫crossover的error，这个是音频输出级最早的经典问题。就是中间一段
两个管子都导通了，这时候输出没有办法follow输入-0.7V
电压取决于上下两管的impedance分压。
其他时候都是只有一管导通，所以就是简单的follower
【在 f****3 的大作中提到】
: 这是答案，我不明白为什么输入1.8至3.2，输出要钳制在2.5V，为什么不是输出一直
: follow输入呐。
| t****1
发帖数: 827 | 9 你不明白那个答案，很正常，因为那个答案是错的，至少是很不严谨。
中间那段上升斜率会相对平缓，但是绝对不可能象那个答案画的那样是一条完全水平的线，让你觉得输出是钳制在某一电压。
【在 f****3 的大作中提到】
: 这是答案，我不明白为什么输入1.8至3.2，输出要钳制在2.5V，为什么不是输出一直
: follow输入呐。
| f****3
发帖数: 502 | 10 多谢回复，但是在corssover区间应该是两个管子都截止吧，不是都导通。
【在 E*****a 的大作中提到】
: 你要去翻一下push-pull stage的书。
: 两端各减掉0.7V你应该是懂的，因为上下都有threshold
: 中间的叫crossover的error，这个是音频输出级最早的经典问题。就是中间一段
: 两个管子都导通了，这时候输出没有办法follow输入-0.7V
: 电压取决于上下两管的impedance分压。
: 其他时候都是只有一管导通，所以就是简单的follower
| | | f****3
发帖数: 502 | 11 为啥我觉得理论上来讲应该是平的呐，找到一个pdf里面仿真的也是平的，假设Vgs小于
Vth后完全截止
http://webpages.eng.wayne.edu/cadence/ECE7570/doc/output.pdf
的线，让你觉得
输出是钳制在某一电压。
【在 t****1 的大作中提到】
: 你不明白那个答案，很正常，因为那个答案是错的，至少是很不严谨。
: 中间那段上升斜率会相对平缓，但是绝对不可能象那个答案画的那样是一条完全水平的线，让你觉得输出是钳制在某一电压。
| E*****a
发帖数: 757 | 12 是的是的，都截止。
【在 f****3 的大作中提到】
: 多谢回复，但是在corssover区间应该是两个管子都截止吧，不是都导通。
| t****1
发帖数: 827 | 13 in your original question, there is no load. both PMOS and NMOS conduct
almost zero current during the entire input range. That is, all the time, PMOS and NMOS are in cut off mode.
the simulation result you are showing has RL=2K.
They are different questions!
Either your original question is wrong, or the answer is wrong. If you still don't understand it, run the simulation by yourself, with NO load. Then tell me what you get. | a****l
发帖数: 8211 | 14 如果电压在中间(2.5)的时候两个管子都是截断的,那么中间vout不就是和两边断开来了
吗?怎么还会有电压?
PMOS and NMOS are in cut off mode.
still don't understand it, run the simulation by yourself, with NO load.
Then tell me what you get.
【在 t****1 的大作中提到】
: in your original question, there is no load. both PMOS and NMOS conduct
: almost zero current during the entire input range. That is, all the time, PMOS and NMOS are in cut off mode.
: the simulation result you are showing has RL=2K.
: They are different questions!
: Either your original question is wrong, or the answer is wrong. If you still don't understand it, run the simulation by yourself, with NO load. Then tell me what you get.
| f****3
发帖数: 502 | 15 我在cadence里面仿的时候没有负载，类似的结果，只是中间不是那么平了，而是率陡
的斜率
这个只是在网上找的图，给大家看一下，我只是想问问物理原理，至于结果是否100%的
准确，无关重要
吧
time, PMOS and NMOS are in cut off mode.
still don't understand it, run the simulation by yourself, with NO load.
Then tell me what you get.
【在 t****1 的大作中提到】
: in your original question, there is no load. both PMOS and NMOS conduct
: almost zero current during the entire input range. That is, all the time, PMOS and NMOS are in cut off mode.
: the simulation result you are showing has RL=2K.
: They are different questions!
: Either your original question is wrong, or the answer is wrong. If you still don't understand it, run the simulation by yourself, with NO load. Then tell me what you get.
| f****3
发帖数: 502 | 16 我重新仿了一下这个pspice的电路，没加负载，一样的结果，所以说负载不是关键。
time, PMOS and NMOS are in cut off mode.
still don't understand it, run the simulation by yourself, with NO load.
Then tell me what you get.
【在 t****1 的大作中提到】
: in your original question, there is no load. both PMOS and NMOS conduct
: almost zero current during the entire input range. That is, all the time, PMOS and NMOS are in cut off mode.
: the simulation result you are showing has RL=2K.
: They are different questions!
: Either your original question is wrong, or the answer is wrong. If you still don't understand it, run the simulation by yourself, with NO load. Then tell me what you get.
| t****1
发帖数: 827 | 17 首先，我很确信，如果没有负载，那个答案是完全错误的，不仅在中段是错误的。现在就讨论你的这个问题吧，和他的题目无关。假设一个电容，有两个端点 A， B。 terminal A 接地，terminal B 接一个开关， 电源通过开关给电容充电，然后断开开关，现在电容 terminal B 完全是floating, 但是terminal B 上还是有电压。
两个管子都是截断
【在 a****l 的大作中提到】
: 如果电压在中间(2.5)的时候两个管子都是截断的,那么中间vout不就是和两边断开来了
: 吗?怎么还会有电压?
:
: PMOS and NMOS are in cut off mode.
: still don't understand it, run the simulation by yourself, with NO load.
: Then tell me what you get.
| t****1
发帖数: 827 | 18 你的cadence仿真结果和我前面告诉你的答案有区别吗？
【在 f****3 的大作中提到】
: 我在cadence里面仿的时候没有负载，类似的结果，只是中间不是那么平了，而是率陡
: 的斜率
: 这个只是在网上找的图，给大家看一下，我只是想问问物理原理，至于结果是否100%的
: 准确，无关重要
: 吧
:
: time, PMOS and NMOS are in cut off mode.
: still don't understand it, run the simulation by yourself, with NO load.
: Then tell me what you get.
| t****1
发帖数: 827 | 19 the original question says: if Vgs<0.7, then cut off. did the devices in your simulation really cut off? no leakage current? Of course not, if you understand what is weak inversion.So, your simulation condition is different from the assumption in that question.
Ok, now let's assume it really cuts off. no leakage current. from your
answer,if vin=0, then vout=0.7, and if vin=0.1then vout is about 0.8v. is
that correct?
My question: when vin increases from 0 to 0.1v, why Vout can not stay at 0.7v. What charges Vout node up? We know that NMOS is off. So NMOS can not do that. PMOS can only sink current. So PMOS can not charge Vout up. So why does Vout node move up? It happens only if there is a resistor tied between vout and 2.5V, so that the resistor will try to pull Vout up. Without Rload, your answer makes no sense. And for the same reason, without Rload, in some input range, the Vout is not defined. It can be any voltage. It depends on how the output parasitic capacitance was previously charged. Now you tell me if Rload is critical or not.
我很确信有负载，无负载，器件运行状态是不一样的，输出曲线也是不一样的。这个我可以从理论上解释出来，也能通过仿真确认。你这孩子请教问题，态度还不大好。好吧，算你赢了，你自己慢慢玩去吧。
【在 f****3 的大作中提到】
: 我重新仿了一下这个pspice的电路，没加负载，一样的结果，所以说负载不是关键。
:
: time, PMOS and NMOS are in cut off mode.
: still don't understand it, run the simulation by yourself, with NO load.
: Then tell me what you get.
| f****3
发帖数: 502 | 20 首先十分感谢你的多次回帖，谢谢！先说明一下，我只是请教问题，没有对任何人的回
复有任何的态
度问题，如果我哪句话让你不爽了，请谅解！
下面说一下这个问题，我又仔细看了一些wiki里面关于crossover的阐述，wiki那张图
上面接
Vdd，下面接Vss，只有负载接Gnd，这样就比较好理解了。
如果|Vin|<0.7，两管截止，输出为0，当Vin>0.7时，上面N管导通，Vout=Vin-0.7，当
Vin<-
0.7时，下面P管导通，Vout=Vin+0.7。当相应于我这到题来讲，上面依然是Vdd，但是
下面接的
GND，所以将GND等效为Vss时，那么输出2.5V即是相应wiki的输出为0，这样就很好理解
为什么不
是一直follow，而在中间需要转换，这是我想问的问题。
但是不好意思，你一直纠结于有无负载，我承认你的思维很严谨，对问题的分析很透彻
，但你并没有
领会我的困惑，呵呵，或许我的困惑很弱智，无需回答，但同时你也并没有说出电路真
正工作的过
程，即使你一开始就给出了很合理的答案。
Anyway,依然非常感谢你的回复，再重申一遍，我对你的回复没有任何的态度上面的问
题，请多包
涵！
in your simulation really cut off? no leakage current? Of course not, if
you understand what is weak inversion.So, your simulation condition is
different from the assumption in that question.
is
at 0.7v. What charges Vout node up? We know that NMOS is off. So NMOS
can not do that. PMOS can only sink current. So PMOS can not charge Vout
up. So why does Vout node move up? It happens only if there is a
resistor tied between vout and 2.5V, so that the resistor will try to
pull Vout up. Without Rload, your answer makes no sense. And for the
same reason, without Rload, in some input range, the Vout is not
defined. It can b: e any voltage. It depends on how the output parasitic
capacitance was previously charged. Now you tell me if Rload is critical
or not.
我可以从理论
上解释出来，也能通过仿真确认。你这孩子请教问题，态度还不大好。好吧，算你赢了
，你自己慢慢
玩去吧。
【在 t****1 的大作中提到】
: the original question says: if Vgs<0.7, then cut off. did the devices in your simulation really cut off? no leakage current? Of course not, if you understand what is weak inversion.So, your simulation condition is different from the assumption in that question.
: Ok, now let's assume it really cuts off. no leakage current. from your
: answer,if vin=0, then vout=0.7, and if vin=0.1then vout is about 0.8v. is
: that correct?
: My question: when vin increases from 0 to 0.1v, why Vout can not stay at 0.7v. What charges Vout node up? We know that NMOS is off. So NMOS can not do that. PMOS can only sink current. So PMOS can not charge Vout up. So why does Vout node move up? It happens only if there is a resistor tied between vout and 2.5V, so that the resistor will try to pull Vout up. Without Rload, your answer makes no sense. And for the same reason, without Rload, in some input range, the Vout is not defined. It can be any voltage. It depends on how the output parasitic capacitance was previously charged. Now you tell me if Rload is critical or not.
: 我很确信有负载，无负载，器件运行状态是不一样的，输出曲线也是不一样的。这个我可以从理论上解释出来，也能通过仿真确认。你这孩子请教问题，态度还不大好。好吧，算你赢了，你自己慢慢玩去吧。
| | | w********u
发帖数: 90 | 21 ｗｉｋｉ里面假设了负载连接到了０ｖ，楼主你的题目里面，必须有负载连接到２．５ｖ才能得到你贴的答案。 | j******e
发帖数: 526 | 22 如果|Vin|<0.7，两管截止，输出为0，当Vin>0.7时，上面N管导通，Vout=Vin-0.7，当
Vin<-
0.7时，下面P管导通，Vout=Vin+0.7。当相应于我这到题来讲，上面依然是Vdd，但是
下面接的
GND，所以将GND等效为Vss时，那么输出2.5V即是相应wiki的输出为0，这样就很好理解
为什么不
是一直follow，而在中间需要转换，这是我想问的问题。
=========================================================
负载很重要，没有负载的话即使Vin>0,7，上面的管子也不会导通，电流没有回路
而且负载所接点位也很重要，因为上下管都截止了，输出点悬空，由负载所接点位决定
，不知道说的对不对 呵呵 | l****o
发帖数: 184 | |
|
