a******e
发帖数: 331 | 1 Intel Corp found a defect in one of its chips, hurting its credibility
during a major product launch and at a time when demand for
microprocessors in PCs is being threatened.
Chipping away: The design flaw comes at a time when Intel faces sluggish
personal computer sales and a major challenge from the exploding
popularity of mobile devices
The company said on Monday it stopped shipments of the chip used in
personal computers with its most advanced Sandy Bridge line of processors
and has already started production of a new version.
Intel said its engineers zeroed in on the newest defect last week after
manufacturers stress-tested the chips with high voltage and temperatures.
The flaw could have stopped computers from being able to communicate with
their hard disk drives or DVD drives. | j******e
发帖数: 526 | 2 转一个网上的分析
Credit goes to Intel for the prompt disclosure and explanation. We can infer
a few things from the information provided.
1. Degradation over time can be associated with NBTI (negative-bias
temperature instability) or HCI (hot-carrier injection). Intel has published
reports on these phenomena in their Journal.
2. It is very difficult to model and simulate these aging effects, and a
65nm chip may have been thought to be immune.
3. Improper biasing, or mismatching of a higher voltage domain to a lower
voltage device can contribute to such problems.
4. Since the device was still functional, but degraded over time (as much
as 3 years according to Intel), my guess is that the metal fix is to
correct a supply rail or bulk connection error. | a******e
发帖数: 331 | 3 The source said it is 22nm design and the defects are in SATA connections.
And I think not likely be NBTI or aging effects which take a few years to
take effect.
More likely is a design fault for multi-voltage issue. | a******e
发帖数: 331 | 4 *********An article on this
If ever EDA needed a ($700M) proof point on their value...
February 2, 2011
As I reported yesterday, Intel announced that a “design error” in a SATA
I/O support chip for the Sandy Bridge processor would cause them to
respin the design… at a cost of $700M! From the information that Intel
provided, it was apparent to me that the problem was most likely a
voltage domain error, i.e. a low voltage device got accidentally hooked
up to a higher voltage supply than it was spec’ed for.
A report on the internet today, if it is credible, confirmed my
speculation:
quoting Intel’s Steve Smith (VP and Director of Intel Client PC
Operations and Enabling) : The problem in the chipset was traced back to
a transistor in the 3Gbps PLL clocking tree. The aforementioned
transistor has a very thin gate oxide, which allows you to turn it on
with a very low voltage. Unfortunately in this case Intel biased the
transistor with too high of a voltage, resulting in higher than expected
leakage current. Depending on the physical characteristics of the
transistor the leakage current here can increase over time which can
ultimately result in this failure on the 3Gbps ports.
Bingo! Exactly as I suspected. Intel’s comments yesterday:
1. Problem was “statistical”
2. Performance degrades over time.
3. The “error” can be fixed by an upper-layer metal mask patch.
In a former life, I was a product marketing manager for two tools that
were designed specifically to find problems like this. Mismatched
voltage domains is, unfortunately, one of the most common causes of
respins in the books. And, sadly, so easily prevented!
There are simple static ERC (electrical rules checkers) that can test
every transistor instance to find any devices with low voltage models
that are hooked up to supply rails that exceed their rating. List price
of these tools?? About 0.01% of what this will cost Intel. (Add a couple
more decimal places with Intel’s discount).
The problem manifested itself as degradation over time, and it was
“statistical”, i.e. not deterministic. This sounds like NBTI, in which
PMOS devices degrade randomly. It could also be HCI, in which NMOS
devices experience charge trapping that alters their threshold voltage
over time.
To test this effect EDA vendors have added features to circuit
simulators that can reproduce “aging”. Work on these techniques began
more than twenty years ago.
This design error may not have been human error at all. It could have
been an error produced by an auto-router that hooked up the bad
transistor. In any case, it’s not a “design error”, it’s a verification
methodology fault.
I bet that gets fixed real quick too!
Posted by Michael Demler on February 2, 2011 | Comments (9) | c****s
发帖数: 2487 | 5 针对这种问题的工具有不少，外边买的，自己攒的，等等等等
但问题是目前的水平下工具们都会有无数的dummy报错，其中的绝大部分都可以waive掉
。可以想象这么个大片子上的报错有多少，当可怜眼睛一行行看下来的时候难免不漏一
两个，如果不巧漏掉的正好有个是值7亿美钞的真正问题。。。
【在 a******e 的大作中提到】
: *********An article on this
: If ever EDA needed a ($700M) proof point on their value...
: February 2, 2011
: As I reported yesterday, Intel announced that a “design error” in a SATA
: I/O support chip for the Sandy Bridge processor would cause them to
: respin the design… at a cost of $700M! From the information that Intel
: provided, it was apparent to me that the problem was most likely a
: voltage domain error, i.e. a low voltage device got accidentally hooked
: up to a higher voltage supply than it was spec’ed for.
: A report on the internet today, if it is credible, confirmed my
|
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