f*********r
发帖数: 674 | 1 跟着我上次的面经再贴些我曾经面过的问题:
Nvidia
1. NAND2 gate, list in order the input vectors that cause most leakage
current to least leakage current.
2. Step response of an LC circuit.
3. draw out a subtractor (A-B) using an adder. How would you implement B-A
using the same circuit?
4. Draw schematic of a D-latch. Explain as you go.
5. Implement NAND, NOR gates using 2:1 mux
6. Aggressor and victim wire. What's the difference when i have a signal at
aggressor switch at sender or receiver?
Startup
1. Implement a | r*****l
发帖数: 24 | 2 Thanks a lot for your sharing | r*********i
发帖数: 67 | | l****s
发帖数: 41 | | H**r
发帖数: 10015 | | f*********r
发帖数: 674 | 6 second and third group are for logic design position :) I didn't do well in
them either... | l*****u
发帖数: 441 | |
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