g*****h
发帖数: 81 | 1 Hi folks,
We have multiple openings in a major wireless fabless design house in
southern California. We are interested in candidates with background in one
or more of the following areas.
- Digital low power design. This could be a position that either works on
power controller design (architecture and RTL implementation) or general low
-power methodology development. Both front-end/back-end experience are
welcome.
- On-chip power regulator design including LDO/SMPS.
- Clocking architecture and IP design
- Timing methodology definition (STA/SSTA/OCV/AOCV etc)
- On-chip power-distribution network and signal integrity analysis.
Both fresh graduates (MS/Ph.D.) and industry veterans are considered. Please
drop me a line if you are interested (站内信件）. Please leave out your
name, contact info, or even your previous employers/universities if you are
concerned about privacy. Just focus on your experience. I'll do some
screening first and move forward with private discussions if there is a fit.
Thanks |
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