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发帖数: 383 | 1 Job Description: Sr. ASIC DFT Engineer
As part of the Central DFT group, you will be responsible for architect,
implementation, verification, and lab bring-up of the DFT and DFM solutions
for the advanced and comprehensive Design for Test/Manufacturing (DFT/DFM)
features for the system on a chip integrated in the industry leading edge
network products.
Core Responsibilities:
• ASIC DFT lead to top level architect, implement and verification of
DFT features including MBIST, Logic BIST, SerdesBIST, IOBIST, JTAG, SCAN/
ATPG, PLL test, and more.
• Write a detailed implementation and verification plan for the DFT
functionality.
• Subchip level and Fullchip DFT simulation to ensure DFT logic will
work.
• Build and run DFT regression to validate any ECO netlists.
• Work with Design team and ASIC vendors to ensure ASIC DFT
requirements are met.
• Provide silicon bring-up support and debug.
Qualifications:
• Minimum: 5 years of relevant experiences
•Knowledge of Verilog and experience with simulators and waveform
debugging tools
•Experience debugging gate-level simulation, both in 0-delay and SDF
environments
•Knowledge of DFT Architecture, including ATPG, JTAG, MBIST & LBIST is
desired but not required
•Knowledge of industry standard DFT and design tools is desired but
not required. Tools such as Synopsys DFT Compiler, Tetramax, PrimeTime, VCS
, ncsim, Encounter Test.
• Experience with one or more scripting languages: Perl, TCL, csh, awk
, python.
• Comfortable editing/using Makefiles
•Ability to conduct experiments during silicon debug, gathering and
analyzing data, and to utilize scripting to support efficient handling of
ATE data
• Excellent problem solving and debug skills.
• Ability to work across the functional teams and the ASIC suppliers.
• Minimum BS in Electrical Engineering/Computer Engineering. MS/Ph.D
in EE preferred.
Work Location Theatre: AMERICAS
Country: United States
State/Province: California
City: San Jose |
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