S***l
发帖数: 383 | 1 my department has one opening for fresh graduate (PhD preferred) in the area
of ASIC DFT (Design for Test).
========================================================
Requirements:
- MS/PHD thesis on test related topics
- clear understanding of key VLSI test topics, such as scan, ATPG,
compression technologies
- programming skills: Verilog/VHDL, Unix scripting(tcl, perl, shell)
Job location is San Jose, CA. Inbox me for details if you are interested.
Need to fill ASAP.
=========================================================
There are also two full-time Senior DFT engineer positions open for persons
with 5-15 yrs experience in the area of DFT. | b****g
发帖数: 7311 | 2 是cisco吗，我认识2个东大的在cisco 做dft
area
【在 S***l 的大作中提到】
: my department has one opening for fresh graduate (PhD preferred) in the area
: of ASIC DFT (Design for Test).
: ========================================================
: Requirements:
: - MS/PHD thesis on test related topics
: - clear understanding of key VLSI test topics, such as scan, ATPG,
: compression technologies
: - programming skills: Verilog/VHDL, Unix scripting(tcl, perl, shell)
: Job location is San Jose, CA. Inbox me for details if you are interested.
: Need to fill ASAP.
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