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发帖数: 25 | 1 I am a digital guy. I have a question on ADC or sample/hold design. This is
used in DC offset measurement/compensation. Can you mixed-signal folks help
answer? Short question is: do they have synchronization flipflops in typical
ADC design? And would the sample-hold hold value stable at arbitrary level
cause receiving flipflops metastable?
I have a voltage comparator in the analog side, the output is driven to the
digital side（synchronous design), to be measured either by sigma-delta or
successi |
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