I***a
发帖数: 704 | 1 我一直是把数字芯片VDD/GND的和source meter的VDD/GND相连，VDD/GND之间没有任何
稳压电容，今天我发现这个可能是问题所在，
VDD和GND之间应该加个稳压电容吗? 如果要的话，多大的电容就可以了？
Thanks. |
E*****a
发帖数: 757 | 2 按说，数字芯片的VDD/GND必须加大电容local bypass
多大？看你电流多大了。你是几伏的芯片？功率多大？
【在 I***a 的大作中提到】
: 我一直是把数字芯片VDD/GND的和source meter的VDD/GND相连，VDD/GND之间没有任何
: 稳压电容，今天我发现这个可能是问题所在，
: VDD和GND之间应该加个稳压电容吗? 如果要的话，多大的电容就可以了？
: Thanks.
|
g*z
发帖数: 124 | 3 If you are fighting ground bounce, you should use some capacitors with ESR
and ESL as small as possible, the capacitance value is not that important.
You can start with some X7R 0603 SMD caps(0.1uF or 0.01uF) or even smaller (
0402), put them as close as possible to the power pins. The keyword here is
ESL and ESR.
The gound bounce voltage V=ESL * deltaI/deltaT
for digital circuits, when switching happens, deltaI/deltaT can be huge, little inductance can cause huge voltage bounce. |
g******u
发帖数: 3060 | 4 100nF ceramic cap close to Vdd is generally enough. |
I***a
发帖数: 704 | 5 1.2 V
Frequency = 25 MHz
功率 = 20 mW
Thanks.
【在 E*****a 的大作中提到】
: 按说，数字芯片的VDD/GND必须加大电容local bypass
: 多大？看你电流多大了。你是几伏的芯片？功率多大？
|
I***a
发帖数: 704 | 6 我做的PCB上面没有留电源电容的位置，我把电源电容放在面包板上可以吗？
thanks. |
g*z
发帖数: 124 | 7 1.2v supply? Are you using 0.13um or lower process? If true, the switching
speed is really fast, I mean, the clock rise time and fall time can be VERY
small , maybe well below 1ns. If this is the case, the ground bounce problem
can be huge if you have no bypassing caps.
bypassing caps SHOULD BE AS CLOSE AS POSSIBLE to the power pin, and ESL
should be as small as possible.
putting caps on the bread board can filter a little bit from the power
supply, but it WILL NOT SOLVE the ground bounce problem. |
I***a
发帖数: 704 | 8 我确实 是用的0.13um,
我弄的是贴片 package的芯片
那我只有把一个电容焊接在vdd header和gnd header之间了？距离pin 5厘米吧，这样
可以不？
电容是越大越好吗？ 是的话我就弄个大的，比如0.22 uF这种够了吧
thanks.
VERY
problem
【在 g*z 的大作中提到】
: 1.2v supply? Are you using 0.13um or lower process? If true, the switching
: speed is really fast, I mean, the clock rise time and fall time can be VERY
: small , maybe well below 1ns. If this is the case, the ground bounce problem
: can be huge if you have no bypassing caps.
: bypassing caps SHOULD BE AS CLOSE AS POSSIBLE to the power pin, and ESL
: should be as small as possible.
: putting caps on the bread board can filter a little bit from the power
: supply, but it WILL NOT SOLVE the ground bounce problem.
|
g*z
发帖数: 124 | 9 0.22uf is enough, you can even settle with smaller (0.1uF, 0.01uF), the key
problem here is how to get low ESL (parasitic inductance). component pins
have parasitic inductance, you need to minimize those parasitic inductance.
generally, the smaller the component size, the smaller the parasitic
inductance.
So in term of ground bounce minimizing,
0402 SMD > 0603 SMD >0805 SMD >1206 SMD >leaded caps.
5cm away from power pin is not close enough, but you can give it a try. If
you have commercial FPGA boards, you can take a look at how close they put
the bypassing caps. |
I***a
发帖数: 704 | 10 这个gound bounce会导致什么后果？
我现在的现象是高频(20M Hz)的时候, glitch 吓死人。 |
|
|
i******n
发帖数: 15 | 11 put gound bounce into google.
google is your friend |
a********s
发帖数: 1876 | 12
靠你这个电路太强悍了，能工作吗?如果是yes,那上帝和你同在。
不知道你怎么面试通过找到工作的，，，，
【在 I***a 的大作中提到】
: 我一直是把数字芯片VDD/GND的和source meter的VDD/GND相连，VDD/GND之间没有任何
: 稳压电容，今天我发现这个可能是问题所在，
: VDD和GND之间应该加个稳压电容吗? 如果要的话，多大的电容就可以了？
: Thanks.
|
I***a
发帖数: 704 | 13 我这里做的所有数字芯片片内都没有de-coupling capacitor,
你的意思是后端设计的时候就要用encounter 的 adddecap命令加上？
数字芯片片内一定要有de-coupling capacitor吗？ 我这里上课做的芯片也没有加啊？
【在 a********s 的大作中提到】
:
: 靠你这个电路太强悍了，能工作吗?如果是yes,那上帝和你同在。
: 不知道你怎么面试通过找到工作的，，，，
|
a********s
发帖数: 1876 | 14
sorry，我理解的测试和你说的测试不一样，是我粗鲁了，抱歉。
【在 I***a 的大作中提到】
: 我这里做的所有数字芯片片内都没有de-coupling capacitor,
: 你的意思是后端设计的时候就要用encounter 的 adddecap命令加上？
: 数字芯片片内一定要有de-coupling capacitor吗？ 我这里上课做的芯片也没有加啊？
|
g*z
发帖数: 124 | 15 When you mentioned about glitch, my first reaction is, are you using the
right way to measure your result?
What is the bandwidth of your scope?
Lot's of rookies think, hey, my clock is 25MHz, so a 100MHZ scope is good
enough. WRONG!
because you are using 0.13um process, the fast clock risetime/falltime put
your signal well beyond the GHz region, you need a scope whose bandwidth is
at least in the GHz range.
OK, you have the GHz scope, are you using the right probe? Don't tell me you
are just using regular probes to measure your squarewave. You need thousand
-dollar worth differential probes.
Now the next question, if you have all those gears, are your signals well
terminated? Because your signal's bandwidth exceed to the GHz range, all
your PCB traces, wires becomes transmission lines. If you don't terminate
them well, you will see ringing, overshooting like hell.
【在 I***a 的大作中提到】
: 这个gound bounce会导致什么后果？
: 我现在的现象是高频(20M Hz)的时候, glitch 吓死人。
|
E*****a
发帖数: 757 | 16 芯片里面是没有的，但是芯片外边紧贴芯片要加
【在 I***a 的大作中提到】
: 我这里做的所有数字芯片片内都没有de-coupling capacitor,
: 你的意思是后端设计的时候就要用encounter 的 adddecap命令加上？
: 数字芯片片内一定要有de-coupling capacitor吗？ 我这里上课做的芯片也没有加啊？
|
I***a
发帖数: 704 | 17 你好，我做的是数字芯片。我用逻辑分析仪测的，Probe是逻辑分析仪自带的。这个逻
辑分析仪采样时间是2ns, glitch是逻辑分析仪上显示的，就是说第1个采样低电平，
2ns后高电平，2ns后低电平
is
you
thousand
【在 g*z 的大作中提到】
: When you mentioned about glitch, my first reaction is, are you using the
: right way to measure your result?
: What is the bandwidth of your scope?
: Lot's of rookies think, hey, my clock is 25MHz, so a 100MHZ scope is good
: enough. WRONG!
: because you are using 0.13um process, the fast clock risetime/falltime put
: your signal well beyond the GHz region, you need a scope whose bandwidth is
: at least in the GHz range.
: OK, you have the GHz scope, are you using the right probe? Don't tell me you
: are just using regular probes to measure your squarewave. You need thousand
|
I***a
发帖数: 704 | 18 我现在最近只能焊到距离引脚2 cm的地方，不能用贴片电容, 而且是直接焊在vdd/gnd
header下面，这样能行不?
thanks.
key
.
【在 g*z 的大作中提到】
: 0.22uf is enough, you can even settle with smaller (0.1uF, 0.01uF), the key
: problem here is how to get low ESL (parasitic inductance). component pins
: have parasitic inductance, you need to minimize those parasitic inductance.
: generally, the smaller the component size, the smaller the parasitic
: inductance.
: So in term of ground bounce minimizing,
: 0402 SMD > 0603 SMD >0805 SMD >1206 SMD >leaded caps.
: 5cm away from power pin is not close enough, but you can give it a try. If
: you have commercial FPGA boards, you can take a look at how close they put
: the bypassing caps.
|
g*z
发帖数: 124 | 19 Any caps with leads has significant parasitic inductance, if you can't get
rid of it, the results won't be good.
the equation is Vbounce =inductance* delta i/ delta t
gnd
【在 I***a 的大作中提到】
: 我现在最近只能焊到距离引脚2 cm的地方，不能用贴片电容, 而且是直接焊在vdd/gnd
: header下面，这样能行不?
: thanks.
:
: key
: .
|
g*z
发帖数: 124 | 20 1) What is the model of 逻辑分析仪?
2) have u terminated your signals?
【在 I***a 的大作中提到】
: 你好，我做的是数字芯片。我用逻辑分析仪测的，Probe是逻辑分析仪自带的。这个逻
: 辑分析仪采样时间是2ns, glitch是逻辑分析仪上显示的，就是说第1个采样低电平，
: 2ns后高电平，2ns后低电平
:
: is
: you
: thousand
|
|
|
g*z
发帖数: 124 | 21 I think what you are seeing is overshooting/undershooting.
You probably have no termination done at all.
here's a quick and easy solution.
put a 100ohm resister between your signal and the probe and your glitches
might go away.
100 ohm
signal--------/\/\/\/\---------------probe |
I***a
发帖数: 704 | 22 (1) Tektronix Logic Analyzer 5204B
http://www2.tek.com/cmswpt/psdetails.lotr?ct=PS&ci=13482&cs=psu&lc=EN
(2) "terminate" 你指的什么？我的输出pin直接drive逻辑分析仪的probe;
pattern generator的probe直接 drive输入pin和逻辑分析仪的probe.
【在 g*z 的大作中提到】
: 1) What is the model of 逻辑分析仪?
: 2) have u terminated your signals?
|
g*z
发帖数: 124 | 23 google high speed termination |
a********s
发帖数: 1876 | 24
gnd
没用，2cm等于没用，100mil以内可能还有点用
【在 I***a 的大作中提到】
: 我现在最近只能焊到距离引脚2 cm的地方，不能用贴片电容, 而且是直接焊在vdd/gnd
: header下面，这样能行不?
: thanks.
:
: key
: .
|
a********s
发帖数: 1876 | 25
他说是阻抗匹配
【在 I***a 的大作中提到】
: (1) Tektronix Logic Analyzer 5204B
: http://www2.tek.com/cmswpt/psdetails.lotr?ct=PS&ci=13482&cs=psu&lc=EN
: (2) "terminate" 你指的什么？我的输出pin直接drive逻辑分析仪的probe;
: pattern generator的probe直接 drive输入pin和逻辑分析仪的probe.
|
E*****a
发帖数: 757 | 26 找个analog guy to help you ba
gnd
【在 I***a 的大作中提到】
: 我现在最近只能焊到距离引脚2 cm的地方，不能用贴片电容, 而且是直接焊在vdd/gnd
: header下面，这样能行不?
: thanks.
:
: key
: .
|
n**x
发帖数: 25 | 27
try put some 0402 SMD decoupling capacitors on the back of your PCB, if you
BGA IC uses some vias to fanout.
【在 I***a 的大作中提到】
: 我一直是把数字芯片VDD/GND的和source meter的VDD/GND相连，VDD/GND之间没有任何
: 稳压电容，今天我发现这个可能是问题所在，
: VDD和GND之间应该加个稳压电容吗? 如果要的话，多大的电容就可以了？
: Thanks.
|
T******T
发帖数: 3066 | 28 Probably need to determine the noise source 1st before your act. Is it due
to crosstalk between your high switching digital signals and or is it really
power supply related due to the high switching current sourced from the
supply as your suspicion indicates ?
If the noise indeed manifests itself on power and ground then decoupling
near the power supply would help to mitigate it. If your glitch is on the
signal only, then decoupling the supply won't help, and instead you should
try to look at possibility of termination related signal reflection, signal
isolation, ground isolation etc.
There are various ways to deal with digital SI issues, ferrite chokes in
series, decoupling caps in shunt (only use if I/O drive strength is strong
and capacitive loading isn't an issue) are amongst common schemes.
Also, if you are trying suppress high frequency noise on either pwr/gnd,
single large de-couple/bypass cap probably won't do it. Better to use
smaller cap values to target the various frequencies components in parallel.
Some of the other posters are right, this could very well be a scope probe
only phantom effect. Passive probes are notoriously misleading when it comes
to analyzing noise. Definitely try to pick up an active or better yet a
high bandwidth active differential probe for your scope. Make sure to place
the scope probe's gnd needle tip as close to the measurement point as
possible to reduce loop inductance.
That way you'll get a much better and true image your digital signal. |
g******u
发帖数: 3060 | 29 I think you deserve some BAOZI for typing so much.
really
【在 T******T 的大作中提到】
: Probably need to determine the noise source 1st before your act. Is it due
: to crosstalk between your high switching digital signals and or is it really
: power supply related due to the high switching current sourced from the
: supply as your suspicion indicates ?
: If the noise indeed manifests itself on power and ground then decoupling
: near the power supply would help to mitigate it. If your glitch is on the
: signal only, then decoupling the supply won't help, and instead you should
: try to look at possibility of termination related signal reflection, signal
: isolation, ground isolation etc.
: There are various ways to deal with digital SI issues, ferrite chokes in
|
T******T
发帖数: 3066 | 30 lol, guess I was being a bit verbose...
So was I smoking crack and gave LZ bunch of mis info ?
【在 g******u 的大作中提到】
: I think you deserve some BAOZI for typing so much.
:
: really
|
