I have two opening in my group:
One principal level with
1. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Another one sr. principal level with
1. CMOS Image pixel design experience
2. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Need Citizenship or PR
Send me email
m****l 发帖数: 17
2
I have two opening in my group:
One principal level with
1. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Another one sr. principal level with
1. CMOS Image pixel design experience
2. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Need Citizenship or PR
Send me email
