m****l 发帖数: 17 | 1 I have two opening in my group:
One principal level with
1. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Another one sr. principal level with
1. CMOS Image pixel design experience
2. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Need Citizenship/PR
Send me email |
m******l 发帖数: 97 | |
p****e 发帖数: 40 | 3 Sorry for no Chinese. Can I ask where the job location is? Thanks! |
m****l 发帖数: 17 | |
m****l 发帖数: 17 | 5 I have two opening in my group:
One principal level with
1. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Another one sr. principal level with
1. CMOS Image pixel design experience
2. design experience of PLL/Serdes
2. analog background
3. 65nm knowledge
Need Citizenship/PR
Send me email |
m******l 发帖数: 97 | |
p****e 发帖数: 40 | 7 Sorry for no Chinese. Can I ask where the job location is? Thanks! |
m****l 发帖数: 17 | |