c*******l
发帖数: 4801 | 1 直观觉得和W/L有关，但仔细想，好像关系又不大，因为起点电流也很高，那小信号
gain一除，倍数好像未必很增加
和什么有关？请教。
thanks |
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x****g
发帖数: 2000 | 2 gm有一堆表达式在那里，
看你固定哪些量，变化什么量了，
gm可以跟（W/L）的n次方成比例，n can be -1,-0.5,0,0.5,1 etc.... |
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r*********e
发帖数: 7 | 7 Gm ~ W/L
Gm per unit gate width, independent of W
gain depends on Gm per unit gate width, not the Gm |
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r*********e
发帖数: 7 | 8 oh...btw
voltage gain does depend on W
current gain and power gain do not |
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m*****t
发帖数: 3477 | 9 en, the Prof was transferred from PSU. The model is jointly developed by PSU
and Philips, so called PSP. (can also be interpreted as surface potential
model)
PSP had been selected over HiSIM (and EKV3.0 BSIM5) as the standard of Next-
Generation MOSFET compact model.
Major advantages over BSIM3/4:
Unified drain current expression valid for all operation regions
Comprehensive small-dimension effect model
Flexible NQS&RF model
Hierarchical model structure
Disadvantages:
Large number of model par |
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f*****0
发帖数: 489 | 10 0.5v trigger is tough to do, as it wouldn't be enough to turn on a bjt.
a few posibilities:
a) you can use some depletion mosfet which conducts at all voltage types.
b) you can use a comparator, preferrably single rail type. like lm311.
c) form a 0.2 - 0.5v supply, and apply it to the base of a npn bjt. type
emitter of your bjt to your control signal, and your relay to the collector.
when the control signal is at 0.5v, the be junction doesn't get enough
signal to turn on the bjt so the relay sta |
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f*****0
发帖数: 489 | 11 the problem with using a depletion type mosfet is that most of those devices
don't have a clear turn on threshold. they gradually turn on and this can
be a death knoll in a switching application like yours. |
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f*****0
发帖数: 489 | 12 another solution is to use germanium transistors. those suckers turn on at 0
.2v vs. 0.6v for a silicon transistor.
that is an almost perfect solution for you: germanium transistors don't turn
completely on. but you can use it to drivea mosfet / silicon tansistor.
the old 3ax31 from China probably go for cents now, and nte has a lot of
germanium transistors. |
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f*****0
发帖数: 489 | 13 mosfet typically has Vgs threshold at 3.5v, p-channel or n-channel. using it
always requires setting up a voltage, which I am not sure is superior. |
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w******u
发帖数: 486 | 14 Why does electric field in MOS device tend to increase as device dimension
shrink
describe the cross-section of a MOSFET with short channel showing the charge
sharing phenomenon
想不出来这2个问题！
翻了半天书，郁闷阿。有人可以帮忙下么
谢了阿 |
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H*****l
发帖数: 702 | 15 能做ultra short gate MOSFET 显然好了。。。。
没智商作ic design的飘过。。。。唉。。。 |
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H*****l
发帖数: 702 | 16 huyou....
现在发现 solid state electronics3大shits(sorry,说重了），就是solar cell,
display( esp.flexible) and LED
low cost industry=== payment for each engineer is lower...since payment
itself is one kind of cost...
啥东西台湾日本做好，啥就挂了。。
可能是说重了，不过这几个我都有同学在不错的学校和group做
大家都觉得终极王道还是老实做classical semiconductor: ultra short gate mosfet
...
hehe,可是不是每个人都够牛而且有命去做的。。。。
发牢骚。。。。 |
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c*******l
发帖数: 4801 | 17 我告诉你个终极王道，那就是不要做device了
做device基本轮不到任何个人startup机会
还是改做电路。如果你够聪明，电路的变化如此多，足够你折腾了
mosfet |
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j***j
发帖数: 324 | 18 各个功率＆电压等级的不一样。
一般1.x - 2伏左右，但给更高的电压rds会更小。 |
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r*********e
发帖数: 281 | 19 要不要考虑noise margin
比如一个1KV的transistor
在Vds=1kV, Vgs=0.5V时是complete pinch-off
Vgs>0.5V, Id就会指数上升
会不会因为一点noise, 导致transistor unintentionally turn-on, 给烧掉?
多谢多谢! |
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j***j
发帖数: 324 | 20 高压mos thres会高一些，而且一般都要加driver电路，会有pull down的resistor的。 |
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r*********e
发帖数: 281 | 21 假设(仅仅是假设,呵呵)off-state leakage和breakdown一样
是不是3V的threshold并不比0.5V的threshold好 |
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g******u
发帖数: 3060 | 22 不知有高手能否教我为什么要有很多low thresold FET的存在？ |
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r*********e
发帖数: 281 | 23 多谢指教
至于GaN, 应该可以很快啦.KV的device上MHz肯定没问题.
关于collapse, toshiba和CREE做到大概300V可以collapse free.在往高压走就不容易了
Vt
collapse的问题搞定了吗？ |
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r*********e
发帖数: 281 | 24 我是新手入门
low threshold的FET不是一般会快一点么? |
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f*****0
发帖数: 489 | 26 well, then you can do the same with pretty much any half bridge drivers, by
providing a steady power supply to the boost pin. since mosfets don't need
much charge after being fully turned on, all you need is to have a voltage
doublter (one 555 + two caps + two diodes).
I just don't know how it works in reality. |
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j********g
发帖数: 23 | 27 做的项目就是个mosfet的仿真，用的fortran.工作方向也应该就是器件模拟之类的，或
者封装测试。 |
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r****e
发帖数: 122 | 29 Ft正比于Gm/Cgs, Gm正比于W/L, Cgs正比于W*L, so Ft 正比于1/L^2. |
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j***j
发帖数: 324 | 32 这个是考虑了short channel effect 以后的结果。
如果L比较大，开始基本还是平方关系。 |
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r****e
发帖数: 122 | 33 两位说得对, 楼主可以参看一下thomas Lee 那本RF书3.6节.
Gm正比于W only, for short channel. |
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le
发帖数: 190 | 34 think about it, frequency is always associated with time.
What time it is? Of course how long charge carrier cross the channel from
source to drain. Now, it's clear that given a velocity if the channel is
shorter than the time needed for an electron to flow is less, and you have
higher cut-off frequency |
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a******w
发帖数: 774 | 35 Noise，对于一个input pair来说，是PMOS or NMOS 的noise更好，请解释主要是什么
东西引起的。如果降低noise，gm需要减少还是增加？
看到这个面试题，希望能有人指教一下 |
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l*****x
发帖数: 3431 | 36 以thermal noise voltage为例吧，正比于KT/gm，所以gm增加好
input pair记得是PMOS好，具体原因忘了 |
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r****e
发帖数: 122 | 38 PMOS 1/f noise 好点， for some unknown reason...
什么 |
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le
发帖数: 190 | 39 For PMOS, its W times L will be bigger to give similar transconductance. So
the oxide-semiconductor interface is said to be smoother, which means it's
less likely to tumble charge carriers.
Another reason may be related with the property of holes. I am not sure... |
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r****e
发帖数: 122 | 40 If I remember well, 1/f comparasion hasn't been related to Gm yet, as
people are comparing Gate *voltage* noise for the same W*L, and Pmos has
larger coefficient....and why it's large seems not clear in physics, we can
guess holes might play a role in it...
So |
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s*******y
发帖数: 4173 | 41 TRANSISTOR有两种噪声，
热噪声肯定是gm大了比较好，
flicker noise我的理解是和gate面积成反比，
pmos是相对比nmos flicker noise小，但那主要
是因为面积大，可那是牺牲的是频率。当然还是
要看你的应用，对那些频段的噪声比较关注，
corner frequency 想在那。 |
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c****s
发帖数: 2487 | 42 同面积的pmos flicker也比nmos小，而且差别还不小
具体原因前面有人说了，unknown, 呵呵
至少我周围的人都说不清楚
网上有文章讨论跟mobility的关系
但这两个应该不直接相关 |
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g*****g
发帖数: 3623 | 43 buck吧
很多芯片现成的，电流不大的话 high side and low side MOSFET integrated in
chip. 有些连补偿都作进去了，plus external inductor and capacitor it will
work..
solution? |
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t*f
发帖数: 114 | 44 你去search一下high voltage power MOSFET的测试方法和电路。甚至power BJT的测试
电路。
或者直接在google scholar上search SiC JFET switching。 |
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H*****l
发帖数: 702 | 45 CETC?
just google No.xx CETC
No.14 is the provider of AESA for Chinese army AWACS and DDG
en. I know a guy who graduated from a U.S. SiC BJT/MOSFET leading group( top
x in this world) back to No.xx CETC like one or two years ago
As the only guy who really know what the fuck is SiC:4H thing, he spent at
least half a year happy hour with the big boss..always travelling for
business and conference...
but he just can not survive through the Atmosphere in China ,you know what I
am talking about
if yo |
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n*l
发帖数: 44 | 46 Grey/Myer 里有关于 mobility degredation 有这么一段话:
A physical reason for (mobility degredation) is that increasing the vertical
electric field forces the carriers in the channel closer to surface of the
silicon, where surface imperfections impede their movement from source to
drain.
这个 "surface imperfection" 怎么理解?.. 它和造成 1/f noise 是同一个
imperfection吗?.. |
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a*******i
发帖数: 11664 | 47 从这段话来看，应该说的是interface scattering
vertical
the |
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n*l
发帖数: 44 | 48 恩, 你说的是对的.. 我又翻了一下 Razavi, 里面说, (this) leads to more carrier
scattering and hence lower mobility.
不过不明白为什么 carrier scattering will become more severe at silicon
surface.. 我想可能是因为 silicon surface 的 crystal lattice 有更多的 defects
... 不知道这样理解对不对.. |
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w********o
发帖数: 10088 | 49 是因为interface rough了，当你在gate加了电压，从source到drain，沿着直线看过去
，个地方的电场不同，导致电子的potential有变化，这个变化导致了scattering
或者极端一点，如果贴着SiO2和Si的界面看过去，有的地方是Si，有的地方是SiO2
这样你的2deg channel不是一个平整的面，你从Capacitance出发可以得到potential的
分布
carrier
defects |
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a*******i
发帖数: 11664 | 50 恩，基本是这样。Si和SiO2的interface会不平，或者存在defects states。对2DEG来
说，他的wavefunction越靠近
interface，受的interface scattering越大。
carrier
defects |
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